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Transistor-Level Update from Cadence at DAC

Transistor-Level Update from Cadence at DAC
by Daniel Payne on 05-20-2013 at 7:47 pm

My 8 years as an IC circuit designer were at the transistor-level, so if that interests you as well then consider what there is to see from Cadence at DAC this year. IC design technology is changing quickly, so keeping up to date is important for your job security and continual education goals.

Here’s what I would recommend attending at Cadence in Booth #2214:

FinFET Design

A Complete, Silicon-validated 20/16/14nm Solution Using Encounter and Virtuoso.
June 3, 12:00PM, Suite 1
June 4, 4:00PM, Suite 1
June 5, 2:00PM, Suite 1

AMS Functional Verification
Low Power Verification of Mixed-signal Designs
June 3, 1:00PM, Suite 1

Mixed-signal Verification
June 5, 11:00AM, Suite 1

AMS Design
Advanced Implementation Techniques for Mixed-signal Designs
June 3, 2:00PM, Suite 1

Custom/AMS Design at Advanced Nodes
June 5, 5:00PM, Suite 1

Designing with Layout Dependent Effects (LDE)
Reducing the Verification Loop for Custom Design
June 4, 10:00AM, Suite 1

SPICE Circuit Simulation
Updated Spectre Platform: Improving Your Verification Throughput
June 4, 3:00PM, Suite 1

Summary
This year Cadence is showing off their transistor-level IC implementation tools as part of sub-flows, instead of just talking about a single EDA tool. You should register in advance if you want to guarantee a spot in the Suite.

lang: en_US

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