Apache is one of the brightest stars in the EDA universe. Paul McLellan has done a nice job covering them before and after the Ansys acquisition. Check out the Apache SemiWiki landing page HERE. The Apache wikis are also very well done and it has been a pleasure working with the Apache marketing team. Expect more innovative things from Apache Ansys right around the corner, believe it.
The proliferation of high-performance mobile devices such as smartphones and tablet computers, along with the trend towards smaller electronic systems, is driving engineers to design and deliver more power-efficient products with extended battery life, while still satisfying increasing performance requirements. Meanwhile, rise in power consumption and electricity costs from the IT infrastructure required to support the growing mobile connectivity world demands more energy-efficient products. In addition, the explosion in system-to-system wireless communications is amplifying the amount of noise within and between ICs, threatening the system with malfunction or failure.
You can tell a lot about a company by their DAC plan. This year Apache lets their customers do the talking:
Low-Power Designs: Optimizing for Power Targets and Ensuring Power Delivery Integrity
Enabling Accurate and Efficient RTL Power Analysis and Optimization Methodology for Low Power Designs – Renesas
Based on industry wide requirements for power reduction, low power design techniques are essential in every stage of an IC’s design. In this presentation, the design flows developed at Renesas in partnership with Apache for RTL power analysis and optimization will be outlined. It will illustrate the effectiveness of the flow to meet the stringent power budget specifications defined in Renesas to meet end system and product requirement. It will highlight the accuracy of the technology and ease-of-use of the methodology. The presentation will touch on the new functions and capabilities Renesas and Apache jointly co-developed and will present the ongoing and future development roadmap of this collaboration.
June 4 @ 12:00 <To Register>
June 6 @ 11:00 <To Register>
Power Noise and Other Simulation Considerations for Energy-efficient SoCs – LSI
Maximizing energy-efficiency has become a key design requirement for many SOC products today. Not only in systems where extending battery life is important, but also increasingly in wall-plugged appliances there is a general trend towards achieving a low energy footprint. One effective way to maximize energy-efficiency is to turn functions off when not in use. A powerful design implementation strategy to achieve this is the use of on-chip power switches, also known as MTCMOS. Introducing on-chip power switches require several trade-offs to be considered with respect to power integrity. First, the additional voltage drop across the switches needs to be understood. Both static IR-drop as well as dynamic voltage drop targets needs to be met in presence of the power switches. At the same time, the leakage across the switches should be minimized in order to maximize energy-efficiency. Second, the on/off switching of functions can result in additional transient current. These so-called rush-in currents cause additional voltage noise in the form of Ldi/dt that need to be well understood. A trade-off often needs to be made between the speed at which a function is turned on/off and the amount of di/dt that is produced in the process. This presentation will review these considerations and highlight a simulation methodology using the RedHawk Advanced Low Power platform. Comparison to SPICE-based simulations was done to qualify the results from the RedHawk analyses.
June 4 @ 15:00 <To Register>
Power Delivery Integrity: On-Chip Power Integrity with Consideration for Parasitic Impact from Package/PCB
A Chip-Package Simulation Methodology for Ultra-Large Low-Power Mobile ICs – Samsung-SSI
This presentation highlights simulation considerations for performing comprehensive on-chip power integrity analysis with package impact. Simulation methodologies for analyzing full-chip dynamic voltage drop in ultra-large mobile ICs with billions of nodes will be covered along with simulation results. As accurate dynamic voltage drop analysis requires the inclusion of appropriate package models, this presentation will provide suggestions on how to achieve this for full-chip dynamic noise analysis. It will also provide guidance for chip and package co-design and validation to achieve faster design closure for these complex mobile SoC products.
June 4 @ 14:00 <To Register>
On-chip Power Integrity Analysis Flow for Very Larg, Highly Complex 28nm Mobile / DTV Designs – Samsung-DT
This presentation covers power integrity challenges of very large IC designs for mobile and DTV applications, especially for designs with large geometry node counts caused by via arrays and fishbone structures. It will introduce a smart power sign-off flow with early analysis capability based on Apache’s RedHawk solution.
June 4 @ 14:00 <To Register>
Power Noise Analysis with Silicon Correlation Results for Complex 32nm ASIC Designs – Ciena
For complex high-speed ASIC design, simulation and analysis of power noise in on-chip power distribution networks (PDN) is important to guarantee first time success. Dynamic voltage drop is the key challenge in today’s low-power, high-current designs. This presentation outlines the PDN design and power integrity simulation for Ciena’s complex 65nm and 32nm ASIC with 30+ million gates. Co-simulation with package/pcb model with decap effect are performed to capture dynamic voltage drop for peak power and high transient current modes. Lab measurement in time and frequency domains were performed on the taped-out design and compared against full-chip gate-level VCD simulation.
June 5 @ 15:00 <To Register>
Analog / Mixed-Signal Designs: Protecting Noise Sensitive Circuitry from Power Noise Impact
Full-chip Substrate Noise Coupling Analysis and Noise Isolation Structure Design Experiments – NXP Semiconductor
A test chip in 65nm has been designed for measuring the benefits of various substrate noise isolation structures. Simulations were performed to measure the efficacy of these structures and compared against the measurement results. The simulated noise levels, in time and frequency domain, have an adequate match with the measured values. Also the trends like impact of increasing data activity on noise level and the effect of protection strategies are predicted correctly. Additionally the result from the full-chip simulation was back-annotated to block level Spice simulations to model the impact of the substrate noise at critical parts of the block.
June 5 @ 11:00 <To Register>
Evaluating Design Options and Trade-offs through Full-chip Substrate and Metal Layer Noise Analysis for a Commercial Image Sensor Chip – Aptina
Modeling and mitigating the noise coupled from high speed digital circuits and I/O pads to sensitive analog circuits can be challenging for any mixed-signal IC design. However, image sensor chips present a unique challenge in this regard as these chips need to operate at high speeds in a variety of customer design configurations. Additionally, the image quality can vary significantly with spatial and temporal variations in the system level noise. A number of factors like the focus on reducing cost and a distributed IP sourcing strategy can limit the ability to control and mitigate such noise. In this presentation, a methodology is outlined which can be used to generate topographic plots of substrate and metal noise. This was used on an Aptina imaging chip to predict the distribution of noise on the chip, and permit design changes to be evaluated.
June 5 @ 11:00
Advanced Reliability Challenges: Effectively Detect and Predict ElectroStatic Discharge (ESD) Failures
Electrostatic Discharge (ESD) Simulation and Sign-off Considerations for Complex GPU and APU Designs – AMD
Electrostatic discharge (ESD) is a well-known cause of failure in integrated circuits. The sudden release of charge within a circuit can induce Joule heating effects capable of melting metal interconnects. And with each new generation of slimmer wires and thinner dielectrics, the potential for ESD-induced failures often fatal ones grows more significant. Additionally, as chips grow larger and more sophisticated, the task of running ESD analysis on a full chip also grows exponentially more complex. This presentation will discuss a methodology to perform full-chip ESD integrity analysis and sign-off coverage through a divide-and-counter technique.
June 5 @ 15:00 <To Register>
A Dynamic Simulation Methodology for Diagnosis and Predictive Simulation of HBM/CDM Events –nVidia
A comprehensive ESD dynamic methodology is developed for failure diagnosis and predictive simulation to achieve design improvements. This methodology focuses on dynamic analysis including modeling of die-level metal grid, substrate grid and well diode, package effective capacitance, and pogo pin. Real HBM and CDM application examples will be illustrated.
June 6 @ 12:00 <To Register>
Chip-Package-System: Analysis and Optimization of High-Speed Interface Across Chip, Package and PCB
Simultaneous SI and PI Analysis for High-speed IO Designs for Mobile Applications – ST-Ericsson
With the current trend to move to higher data rate wireless applications, the power delivery network of digital high speed interfaces is more and more critical and must be electrically validated during the design phases. These analyses require the modeling of the complete system from board components to IO drivers and their associated parasitics and switching noise. This presentation will give an overview of a simulation methodology that simultaneously includes the switching impact of an entire bank of IO cells along with the associated IO ring PDN parasitics, the package and PCB parasitics including the coupling between power and signal nets and the parasitics of the termination logic.
June 5 @ 1:00 <To Register>
System-level Power Noise Analysis and Optimization with Measurement Correlation Results for Multiple DRAMs with TSV – Samsung-DRAM
In this presentation, a new SSN simulation methodology will be described for an integrated chip-package-PCB system. The proposed SSN analysis process includes modeling and co-simulation methods for chip/package/PCB. The process is verified on a design with several DRAMs mounted on memory module PCB running refresh operation. The experiment shows exceptionally accurate results between simulation and measurement for SSN and Zin comparison. Using the proposed technique, SSN was analyzed for designs with various configurations of DRAMs and decoupling capacitors with TSV (Through Silicon Via).
June 5 @ 1:00 <To Register>
3D-IC Designs: Understanding 3D Architecture and Considerations for Simulating 3D/Stacked-Die Designs
Considerations for Designing and Simulating Memory Interfaces for 3D/Stacked-die Designs – UCSD
This presentation will cover the simulation and design considerations for choosing a Memory Interface. It will discuss the design and analysis of wide-I/O vs. asynchronous serial I/O, the evolution and pros and cons of wide-I/O, and use of CACTI for I/O models. It will also cover the applications of 3D to memory interface calculator and provide comparison of hybrid memory cube vs. standard TSS. The discussion will summarize how to account for power and signal integrity concerns and simulate and sign-off 3D memory interfaces.
June 6 @ 2:00 <To Register>
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