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Power Issues for Chip and Board: webinar

Power Issues for Chip and Board: webinar
by Paul McLellan on 03-10-2012 at 4:24 pm

 Last month Brian Bailey at EDN moderated an interesting webinar about power issues. Unusually, it combined two different domains: doing things by modeling and actually taking measurements off real chips and boards. The two participants were Arvind Shanmugavel from the Apache subsidiary of Ansys, and Randy White from Tektronix.

Nobody needs me to tell them that power is a major issue for chip and board design. This webinar wasn’t so much about how to reduce power, important though that is, but more about how to deliver power and analyze what is being delivered, and then take measurements to see what is really happening. With low noise margins but a transistor threshold voltage that cannot change much, issues with the power supply such as voltage droop will cause systems to fail.

One of the biggest areas is active state power management whereby the software works with the underlying chip to control things like voltage island and power down blocks. If a block doesn’t need to produce its result fast then why bother to run it in high speed/high power mode. The challenge with this is that the transitions, changing the voltage of a block or powering it on or off produce major transients in the power network. The most extreme is power up a block that was powered down. Done naively the inrush current will cause the voltage to drop to the whole chip and so the received wisdom is to power the block up slowly (which, of course, means you know far enough in advance that you’ll need it) and only connect the main power transistors when the block is up to the supply voltage (so no inrush current).

For me the most interesting parts were Randy’s comments about measuring everything since it’s not an area I know lots about (I’m a software guy by background). At GHz performance levels, everything affects everything. Every probe has its own inductance, capacitance, resistance and so affects the measurement. I had no idea that Tektronix provides Spice models of all their probes so that you can work out what you expect to see on the scope given which probes you are using, since it differs from what the simulation says the actual signal value will be.

Arvind had an interesting example showing how the thermal map of a die varies dependent on the package. And not just due to thermal aspects of the package but transient power supply effects too.

We used to have a lot of margin on power supplies, with as much as 25% of tolerance. Now, especially in battery powered mobile devices it can be as low as 5%. This requires both an accurate power model and accurate ways of taking measurements off the actual devices without, Heisenberg style, perturbing the actual system too much.

The webinar is here.

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