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WIKI Multi FPGA Design Partitioning 800x100 
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Aldec
Posted on by Bernard Murphy

Webinar: Fast-Track to Riviera-PRO

Webinar: Fast-Track to Riviera-PRO
by Bernard Murphy on 08-11-2017 at 7:00 am
Categories: Aldec, EDA, FPGA

Whether you’re right out of college, starting on your first design, a burn-and-churn designer thinking there must be a better way or an ASIC designer wanting to do a little prototyping, this webinar may be for you. It’s a fast start on using the Aldec Riviera-PRO platform for verification setup, run and debug, and more. There are a lot of tools you have to learn in your job and manuals are a painful way to get there. Fast-Track guidance is the best way to get up and running quickly.

REGISTER NOW for this Webinar on August 17[SUP]th[/SUP] from 11:00AM to 12:00PM PDT

Abstract
Riviera-PRO™ Advanced Verification Platform addresses the verification needs of engineers crafting tomorrow’s cutting-edge FPGA and SoC devices. Riviera-PRO enables the ultimate testbench productivity, reusability, and automation by combining the high-performance simulation engine, advanced debugging capabilities at different levels of abstraction, and support for the latest Language and Verification Library Standards.

This first webinar of a two-part “Fast Track” series is designed to help functional verification engineers get up to speed quickly with Design Management and Design Entry in Riviera-PRO. Includes tips and tricks to enable easier debugging of designs. Also covers how to run Simulations and handling waveforms.

REGISTER NOW for this Webinar on August 17[SUP]th[/SUP] from 11:00AM to 12:00PM PDT

Agenda

  • Introduction
  • Live Demo
  • Spec-TRACER™ demo
  • Conclusion
  • Q&A

Presenter Bio
Sunil Sahoo provides support for customers exploring simulation tools as an Aldec Applications Engineer. His practical engineering experience includes areas in, Digital Designing, Functional Verification and Wireless Communications. He has worked in wide range of engineering positions including Digital Design Engineer, Verification Engineer and Applications Engineer. He received his B.S. in Electronics and Communications Engineering from VIT University, India in 2008 and M.S in Computer Engineering from Villanova University, PA in 2010.

About Aldec
Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, CDC Verification, IP Cores, Requirements Lifecycle Management, Embedded, DO-254 Functional Verification and Military/Aerospace solutions. https://www.aldec.com/

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