IC Packaging Technology
Integrated Circuit packaging has always been integral to IC performance and functionality. An IC package serves many purposes: 1) pitch conversion between the fine features of the IC die and the system level interconnection; 2) chemical, environmental and mechanical protection; 3) heat transfer; 4) power, ground and signal distribution between the die and system; 5) handling robustness; and 6) die identification among many others. Numerous critical technologies have been developed to serve these functions; technologies that continue to advance with each new requirement for cost reduction, space savings, higher speed electrical performance, finer pitch, die surface fragility, new reliability requirements, and new applications. Packaging engineers must fully understand these technologies to design and fabricate future high-performance packages with high yields at exceptional low-costs to give their company a critical competitive advantage.
IC Packaging Technology is a 2-day course that details the vital technologies required to construct IC packages in a reliable, cost effective, and quick time to market fashion. When completed, the participant will understand the wide array of technologies available; how technologies interact; what choices must be made for a high-performance product vs. a consumer device; and how such choices impact the manufacturability, functionality, and reliability of the finished product. An emphasis will be given to manufacturing; processes; and materials selection, tailoring, and development. Each fundamental package family will be discussed, including flip chip area array technologies, Wafer Level Packaging (WLP), Fan-Out Wafer Level Packaging (FO-WLP), and the latest Through Silicon Via (TSV) developments. Additionally, future directions for each package technology will be highlighted, along with challenges that must be surmounted to succeed.
What Will I Learn By Taking This Class?
By focusing on current issues in packaging technology, participants will learn why advances in the industry are occurring along certain lines and not others. Participants will learn about semiconductor packaging without having to delve heavily into the complex physics and materials science that normally accompany this discipline. Participants will learn basic, but powerful aspects about the semiconductor packaging. This skill-building series is divided into four segments:
- Molded Package Technologies. Participants will learn the fundamentals of molding critical to leaded, leadless, and area array packaging, enabling them to eliminate problems such as flash, incomplete fill, and wire sweep.
- Flip Chip Technologies. Participants will learn the fundamentals of plating, bumping, reflow, underfill, and substrate technologies that are required for both high performance and portable products.
- Wafer Level Packages. Participants will learn the newest technologies that enable the increasingly popular Wafer Chip Scale Packages (WCSPs) and Fan-Out Wafer Level Packages (FO-WLPs).
- Through Silicon Via Packages and Future Directions. Participants will understand the latest advances in the recently productized TSV technology, as well as future directions that will lead to the products of tomorrow.
Course Objectives
- The course will supply participants with an in-depth understanding of package technologies, current and future.
- Potential defects associated with each package technology will be highlighted to enable the participants to identify and eliminate such issues in product from both internal assembly and OSAT houses.
- Cu and solder plating technologies will be described with special emphasis on package applications in Through Silicon Vias (TSVs) and Cu pillars for FO-WLPs. Emphasis will be placed on eliminating issues such as reliability, non-uniformity, void-free thermal aging performance, and contamination-free interfaces.
- New package processes employed in TSV production will be described, along with current cost reduction thrusts, to enable the participants to understand the advantages and limits of the technologies.
- Temporary bonding and wafer thinning processes will be highlighted, as well as the cost reduction approaches currently being pursued to enable wider adoption of TSV packages.
- The trade-offs between silicon, glass, and organic interposers will be highlighted, along with the processes used for each.
- Participants will gain an understanding of the surface mount technologies that enable today’s fine pitch products.
- This course will provide detailed references for participants to study and further deepen their understanding.
Why Huawei Says It Will Match TSMC’s Most Advanced Chips by 2031