At the recent DAC conference in Austin I attended a panel discussion over lunch where engineers from four companies talked about how they approached mixed-signal design and verification challenges for automotive and IoT systems. It seems like 2017 was the year of automotive at DAC, while in 2016 it was all about IoT. Both segments are attractive because of their size (Automotive) and growth potential (IoT). The panelists included:
- Pierluigi Daglio, STMicroelectronics, AMS Design Verification Manager
- Suresh Jayaraman, Amkor
- Goeran Jerke, Bosch, EDA R&D
- Vinod Kariat, Cadence, Custom Analysis Products
Source: Paul McLellan
Pierluigi said that business at his company is good with some $6.97B in revenues for 2016 made possible by an engineering staff of 7,500. They have a Smart Power division which tends to use their BCD (Bipolar, CMOS, DMOS) technology for a wide range of products including automotive. With a 110nm process they can handle the high voltage requirements inside of cars. They also have PCM (Phase Change Memory) technology, digital, analog and memory IP used in their products.
His wish list for improvements include:
- FastSPICE circuit simulation speedup
- Adaptive AMS converter IP
- Electrically aware design
- Fast parasitic estimation
- Safe Operating Area analysis
- Post-layout signoff analysis
Suresh positioned his company as the #2 OSAT (Offshore Assembly and Test) vendor in the world, and they are serving customers in several segments: Mobility, Consumer/IT, Automotive, HPC, System in Package (SiP). An emerging trend for Amkor is the Fan Out Wafer Level Packaging (FOWLP) along with advanced wafer SiP.
Goeran told us that Bosch is best know for its range of ICs for automotive and consumer goods like Smart Phones. He sees many challenges for mixed-signal designs:
- Power train electrification
- Connectivity (car2car)
- Teraflops of processing in self-driving cars
- Complexity between IC, MEMs, PCB and packaging
- Learning new EDA tools and design flows
At Bosch they are taking more of a systems design approach now, instead of just producing components. They need to have requirements tracing across all software tools, and want a closer collaboration with EDA vendors.
The final panelist was Vinod and he shared that Cadence is spending up to 40% of revenue on R&D. Their challenge is to enable automotive and IoT design for companies doing mixed-signal projects with their EDA tools and IP. Cadence offers a range of tools and then partners with other vendors like: PTC, Dassault, MathWorks, Arrow, Coventor, Lumerical and PhoeniX.
Following the opening remarks the panelists went to an open Q&A format with attendees.
Q: How do you balance the number of jobs needed to be run?
ST – We need the speed of simulation to be fast, even taking digital regression ideas into analog (ADE Verifier) – start from Excel or Word then go into simulations comparing results versus specification. We use a compute farm to manage EDA runs.
Bosch – We have a similar approach as STM. We take requirements into the design process. Run regressions and they can take weeks to complete. We’re now using a system-level modeling approach too. We do need simulation that scales better. Terabytes of data being produced, so we need better ways to analyze the results.
Cadence – There are new areas like grading and fault testing for reliability of mixed-signal systems.
Bosch – We cannot simulate every silicon effect, so we need more ERC static checks along with simulation.
Q: Do automakers and SAE step in and define a tool flow in the future?
Bosch – vendors want to know what happens if we change something in our system? SAE isn’t interested in tools, just setting guidelines for safety.
Q: With AMS in self-driving cars, does Cadence offer some features to make tools work with DOORs or Enterprise Architect?
Cadence – We do some things within our own cockpits for simulation, but don’t yet integrate with a DOORs type of tool for systems requirements.
Q: Circuit simulation takes too much time, so is not practical for comprehensive testing. What do you recommend?
Cadence – Fault simulation and fault analysis are an active topic today for automotive. Static checking approaches make sense for new analysis to complement functional simulation.
Bosch – Yes, we do need analog fault simulation, it’s an active research area.
ST – I believe in static checks for the future to ensure correctness, and ERC to complement dynamic simulation. We really want analog fault injection at the block (take days to simulate) and system levels.
Q: Cadence – does package selection take place much earlier today?
Amkor – Yes, it’s a much earlier decision today to get the proper package for design.
Bosch – Packaging tools need to pick up failure mechanisms earlier like stress.
Q: How popular are multi-die system solutions?
Amkor – It’s growing because digital and analog are often separate chips. Large companies are mixing dies to get the fastest time to market.
ST – It’s been difficult to simulate package and board together because of format conflicts.
Q: How is the focus on Automotive changing device models and aging?
Prof. Sayers Salahuddin, UC Berkeley – all requests are based on transistor models. We can quickly create new device models, although simple models often are acceptable.
Q: For the reliability of automotive components, how do they impact design?
Bosch – We have to trust the EDA tools enough that the simulation results are proper. We tend to live with uncertainty, so we tend to design with redundancy.
ST – looking for better Monte Carlo simulation approaches to improve reliability.
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