Updated tool cuts through DO-254 V&V chaos

Audits. The mere mention of the word keeps project managers up at night and sends most designers running. However, in the case of FPGA designs seeking DO-254 compliance, the product doesn’t ship until the audit is complete – there is no avoiding it, or skating around it. The process goes much easier when design artifacts are transparent, rapidly available to answer any question an auditor can pose.

Transparency is a problem, because rarely are the design artifacts in an FPGA design flow in a nice clean repository. More than likely, multiple tools are in use each producing a stream of design data. Some organizations use IBM DOORS, but many times design requirements and test results are in a simple Microsoft Word document. FPGA design and test bench source code can be in a variety of formats. Test coverage data is often some other format. The pile of data can be quite large, and just visualizing traceability can be daunting.

Nothing causes audit chaos faster than inability to pull up data for a particular item quickly, especially when tough questions and intense schedule pressure exist. Many teams have figured out use of a document repository to control file storage expedites the process, but raw files do little for search and extraction of validation and verification (V&V) artifacts without some kind of automation. A lengthy list of issues, even if they have supporting artifacts somewhere in the organization, can take days or even weeks for teams to chase down, delaying a project and adding to frustration for project managers and designers.

Conversely, DO-254 auditors are in a much better mood when they can see what is going on, and questions get at least some documented answer fairly quickly. Keep in mind, most audit teams want to help you to pass as long as they are convinced processes were documented and followed and results supporting objectives are traceable. Auditors generally would like nothing more than to review a project on site and leave with only a few minor items that can be resolved via email or conference call, and let everyone get back to work.

We’ve introduced Aldec Spec-TRACER before as a requirements traceability tool. The latest 2015.12 release takes DO-254 V&V data management to a new level. The new features are essentially data mining, parsing design data from a variety of formats into a single view that can guide the audit step by step. For instance, requirements can be pulled from .doc or .docx files, and code parsed from .vhd, .v, .sv, or .psl files using regular expressions and captured automatically. The tool also reads the Aldec Coverage Database (.acdb) for simulation results.

The bigger an FPGA design is, the more vital a project management tool like Spec-TRACER 2015.12 becomes in a DO-254 compliance scenario. Two nice features in the new release are a sample project providing templates showing how to use the parsers to build traceability, and video tutorials with expert guidance on creating a project, building traceability, and conducting impact analysis. This helps first-timers set up the tool, and more experienced teams smooth out their preparation for an audit.

Aldec has a live webinar coming up in March on managing the DO-254 V&V challenge with Louie De Luna, following up on their earlier recorded event introducing the V&V objectives.

Efficient Management of DO-254 Validation and Verification

Visit the Aldec website for more details on the Spec-TRACER 2015.12 release.

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