Learning an HDL Simulator

Learning an HDL language or an HDL simulator are two different things, so I wanted to see what was available for learning a vendor-specific HDL simulator. I’ve already taught Verilog as an instructor using both ModelSim and Active-HDL simulators, however we only used a handful of commands in the class and labs in order to focus on the language. I found out that an engineer at Aldeccreated a three part webinar on learning their HDL simulator, Active-HDL, so I watched part one, a 65 minutes video. The basic idea was to cover several key simulator concepts:

• Designs and Workspaces
• Library management
• HDL editor commands

A workspace holds all of your design together along with library information, source files, scripts and waveform files. As you create your new design there will be many folders and files created automatically that you can view in Explorer on a Windows machine:

A single file is used to define your Workspace, and it’s an ASCII file that can be viewed with Notepad or even edited, and the extension is .aws (Workspace). Each design file is saved with an extension of .adf (Aldec Design File), library files are saved with an extension of .cfg (Configuration). All HDL source and schematic files are saved in a folder called SRC. Double-clicking your Workspace file invokes the HDL simulator and you can quickly see a Design Browser with one design file on the left side and a design flow on the right side of Active-HDL. This example workspace was named PressController.

Active-HDL supports design entry as HDL or other language source code (VHDL, SystemVerilog, Verilog, SystemC, PSL, OVA, Tcl, Perl, Macro, Text, SDF, EDIF, C++), Block Diagram Editor, or a State Diagram Editor. So your designs can be a mixture of all these different design entry styles, connected together.

You can quickly create a macro to compile all of your source HDL files in the correct order, then run simulation, all using a GUI dialog, with no manual editing required. Each source file has properties where you can define which language library version to use for compiling, along with options. In this case they have a VHDL source file and are using VHDL 1076-2002 for the library choice:

You can create your own compiled libraries using a Wizard in the GUI by adding HDL source files, and then the new library shows up in the Design Browser.

An entire design can be Archived and then later on Restored using the GUI if you need to share designs with other engineers. As you make an Archive then a new Design Status Folder appears in the Design Browser that catalogs the status of your design changes and uses a timestamp for the folder name. Each of the status files are ASCII test files that conveniently summarize your design, libraries and files.

If you don’t like the default directory structure from Active-HDL then there ‘s a way to define your own folder structure that conforms to your methodology. A design structure file can be shared between team members as design_structure.cfg, and even shared on the network for a common environment.

When using schematics or the block diagram editor there’s a library manager GUI which shows vendor-compiled libraries that are available for use in your design to do things like importing or exporting symbols.

The Active-HDL simulator has a command line in the Console window where you can type interactive commands to see library contents or even automate common tasks. Auto-complete makes typing even faster in the Console.

Opening your source code invokes the Code Browser which has both color coding in the editor and a browsing window working together.

Any syntax typos may be immediately highlighted in both the text editor and Code Browser windows without waiting for a separate compile step, it’s your choice if you want to wait until a Save before seeing errors or warnings. Code can be automatically color-coded or formatted, and of course you can define your own color scheme and formatting to make pretty source code that fits your style. Mouse strokes are another novel feature that can improve designer productivity by connecting strokes to commonly used commands.

Q&A

Q: Can you print out the design status reports?

Yes, in text, HTML or PDF formats.:

Q: What gets created when you synthesize and P&R for an Altera design?

A folder is created with all detailed files, including SDF file for timing simulation.

Q: Does the Code Browser require a separate license?

No, it’s available in all configurations.

Q: How about getting version control in a future release of Active-HDL?

With the archive command you get some level of version control.

Summary

The entire webinar is 65 minutes long and it will get you up to speed quickly in learning how to use Active-HDL on a new design. One thing to note is that the first 1:36 of this video can be skipped.

Relatived Videos

• Fast Track to Active-HDL, Part 2
• Fast Track to Active-HDL, Part 3

lang: en_US