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WIKI Multi FPGA Design Partitioning 800x100
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Webinar: Making a Simple, Structured and Efficient VHDL Testbench

Webinar: Making a Simple, Structured and Efficient VHDL Testbench
by Daniel Nenni on 04-16-2013 at 1:47 am

Most simple testbenches have close to no structure, are terrible to modify and hopeless to understand. They often take far too much time to implement and provide close to no support when debugging potential problems. This webinar will demonstrate how to build a far better testbench with respect to all these issues – in significantly less time. The webinar will also explain how this verification approach results in reduced design and debug time with the help of an open-source testbench infrastructure library.

Guest Presenter: Espen Tallaksen, Bitvis CEO and Principal FPGA/ASIC Developer
[TABLE] cellpadding=”2″ cellspacing=”2″ style=”width: 90%”
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| Bitvis is a vendor independent Design Centre with competent designers, experienced in Embedded Software and FPGA/ASIC development and verification.
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Agenda

  • Making a verification specification
  • Defining your testbench architecture and concept
  • General testbench infrastructure library and methods
  • Implementing the testbench architecture
  • Implementing testcases

For more information, please visit http://www.aldec.com/events

Aldec Inc., headquartered in Henderson, Nevada, is an industry leader in Electronic Design Verification and offers a patented technology suite including: RTL Design, RTL Simulators, Hardware-Assisted Verification, SoC and ASIC Prototyping, Design Rule Checking, IP Cores, DO-254 Functional Verification and Military/Aerospace solutions.
www.aldec.com

lang: en_US


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