This is the 15th anniversary of the TSMC Open Innovation Platform (OIP). The OIP Ecosystem Forum will kick off on September 27th in Santa Clara, California and continue around the world for the next two months in person and on-line in North America, Europe, China, Japan, Taiwan, and Israel. These are THE most attended semiconductor… Read More
Semiconductor Intellectual Property
CEO Interview: Koen Verhaege, CEO of Sofics
Koen Verhaege, CEO of Sofics (“Solutions for ICs”), has developed his career first as an engineer, later as a business leader and entrepreneur, working on IP development and valorisation. Koen’s technical accomplishments, publications and patents are in the field of on-chip ESD protection design.
Today, Koen… Read More
Deeper RISC-V pipeline plows through vector-scalar loops
Many modern processor performance benchmarks rely on as many as three levels of cache staying continuously fed. Yet, new data-intensive applications like multithreaded generative AI and 4K image processing often break conventional caching, leaving the expensive execution units behind them stalled. A while back, Semidynamics… Read More
Successful Inter-Op Verification of Enterprise Flash Controller with ONFI 5.1 PHY IP
In an era defined by digital transformation and data-intensive applications, the solid-state device (SSD) market has emerged as a critical player in reshaping storage solutions. While there are several types of non-volatile memories, each with its own unique characteristics and use cases, Flash memory is increasingly overtaking… Read More
WEBINAR: Understanding TSN and its use cases for Aviation, Aerospace and Defence
This webinar will introduce Time-Sensitive Networking (TSN) and unveil how TSN can provide value in aviation, aerospace and defence.
TSN is a new set of standard extensions based on the IEEE 802.1 and IEEE 802.3 Ethernet standards. It is designed to provide deterministic guarantees on Quality of Service (QoS) metrics and reliability… Read More
Extending RISC-V for accelerating FIR and median filters
RISC-V presents a unique opportunity for designers to extend the microarchitecture with custom instructions. One possible application is digital signal filtering using finite impulse response (FIR) or median filters, potential algorithms for carrier demodulation schemes in communications systems like 5G. Codasip application… Read More
Fitting GPT into Edge Devices, Why and How
It is tempting to think that everything GPT-related is just chasing the publicity bandwagon and that articles on the topic, especially with evidently impossible claims (as in this case), are simply clickbait. In fact, there are practical reasons for hosting at least a subset of these large language models (LLMs) on edge devices… Read More
Interface IP in 2022: 22% YoY growth still data-centric driven
We have shown in the “Design IP Report” 2022 that the market share of the wired Interface IP category is a growing part of the total IP, and that this trend is confirmed year after year. The interface IP category has moved from 18% share in 2017 to 25% in 2022.
During the 2010-decade, smartphone was the strong driver for the IP industry,… Read More
The Incredible Journey of Analog Bits Through the Eyes of Mahesh Tirupattur
If you’ve designed a chip with analog content (and who hasn’t), you know Analog Bits. Along the way, you likely met Mahesh. If you are a lover of fine wines, you probably know Mahesh quite well. More on that later. I got the opportunity to speak with him recently about what he’s been up to, both now and over the past few years. It’s a story… Read More
RISC-V 64 bit IP for High Performance
RISC-V as an Instruction Set Architecture (ISA) has grown quickly in commercial importance and relevance since its release to the open community in 2015, attracting many IP vendors that now provide a variety of RTL cores. Roger Espasa, CEO and Founder of Semidynamics, has presented at RISC-V events on how their IP is customized… Read More


Disaggregating AI Compute to Break the Tokens Barrier