A large part of the effort in designing SOCs has shifted to the integration of their constituent IP blocks. Many IP blocks used in SOCs come as ready to use components and the real work has become making them work together. Network on Chip (NoC) has been a huge help in this task, handling the interconnections between blocks and planning… Read More
Semiconductor Intellectual Property
Measuring Up 7nm IP
The Linley Group is an industry-leading source for independent technology analysis of semiconductors for networking, communications, mobile, and data-center applications. Their Microprocessor Report is widely read as a source of un-biased, no-nonsense analysis of technologies and trends. So, when they dig into something… Read More
Enabling Complex System Design Environment
Deterministic, yet versatile. Robust and integrated, yet user-friendly and easily customizable. Those are some desirable characteristics of an EDA solution as the boundaries of our design optimization, verification and analysis keep shifting. A left shift driven by a time-to-market schedule compression, while the process… Read More
eSilicon and SiFive partner for Next-Generation SerDes IP
While writing “Mobile Unleashed: The Origin and Evolution of ARM Processors In Our Devices” it was very clear to me that ARM was an IP phenomenon that I did not believe would ever be repeated. Clearly I was wrong as we now have RISC-V with an incredible adoption rate, a full fledged ecosystem, and top tier implementers… Read More
Timing Channel Attacks are Your Problem Too
You’ve heard about Meltdown and Spectre and you know they’re really bad security bugs (in different ways). If you’ve dug deeper, you know that these problems are related to the speculative execution common in modern processors, and if you dug deeper still you may have learned that underlying both problems are exploits called timing… Read More
Netspeed and NSITEXE talk about automotive design trends at 55DAC
DAC is where both sides of the design equation come together for discussion and learning. This is what makes attending DAC discussion panels so interesting; you are going to hear from providers of tools, methodologies and IP as well as those who need to use them to deliver working solutions. There are few places where the interplay… Read More
Deep learning fueling the AI revolution with Interlaken IP Subsystem
AI is revolutionizing and transforming virtually every industry in the digital world. Advances in computing power and deep learning have enabled AI to reach a tipping point toward major disruption and rapid advancement. However, these applications require much higher performance and bandwidth requiring new kinds of IP and… Read More
Low Cost Power NB-IoT Solution? Fusion F1 DSP based Modem!
Supporting NB-IoT requires low cost (optimized silicon footprint) and ultra-low power solution to cope with IoT device requirement. Cadence Fusion F1 DSP IP has been integrated in modem IC by two new customers, Xinyi and Rafael, gaining traction in NB-IoT market. These design-win builds on previous momentum: software GPS solution… Read More
Optimization and Reliability for FinFET designs at #55DAC
TSMC is the leading foundry worldwide and they make a big splash each year at the DAC exhibit and conference, so I stopped by their theatre area during the presentation from IP vendor Moortec to see what’s new this year. Stephen Crosher was the presenter from Moortec and we had exchanged emails before, so this was the first time… Read More
Keeping Pace With 5nm Heartbeat
A Phase-Locked Loop (PLL) gives design a heartbeat. Despite its minute footprint, it has many purposes such as being part of the clock generation circuits, on-chip digital temperature sensor, process control monitoring in the scribe-line or as baseline circuitry to facilitate an effective measurement of the design’s power… Read More


Intel and TSMC Take Different Paths to High-NA EUV