WP_Term Object
    [term_id] => 4
    [name] => Open-Silicon
    [slug] => open-silicon
    [term_group] => 0
    [term_taxonomy_id] => 4
    [taxonomy] => category
    [description] => 
    [parent] => 386
    [count] => 41
    [filter] => raw
    [cat_ID] => 4
    [category_count] => 41
    [category_description] => 
    [cat_name] => Open-Silicon
    [category_nicename] => open-silicon
    [category_parent] => 386

RISC-V End to End Solutions for HPC and Networking

RISC-V End to End Solutions for HPC and Networking
by Daniel Nenni on 11-30-2018 at 12:00 pm

22685-open-silion-hbm2.jpgSemiconductor IP is one of the more exciting and most viewed topics we cover on SemiWiki, it has been that way since we began in 2011 and that trend will continue indefinitely, my opinion.

Semiconductor IP: Total Blogs: 640: Total Views: 3253751: Average: 5084

Based on the design starts we track, Cloud Computing is a leading semiconductor driver so High Performance Computing (HPC) and Networking IP development and deployment will closely follow including High Bandwidth Memory (HMB2) and Serializer-Deserializer (SerDes) IP.

Specifically, higher memory bandwidth at lower power and technical capabilities (2.5D Interposer-based ASIC design in combination with the new JEDEC HBM Gen2 standard). It needs the integration of significant capacities of high-bandwidth (up-to 256GB/s for an 8-channel, 8Gb memory stack implementation) and low latency memory inside the ASIC package. Open-Silicon’s full IP subsystem solution includes an HBM2 controller, PHY and interposer I/O, and completes the critical components needed for the successful integration of HBM2 memory into ASIC system-in-package (SiP) designs.

One of the more exciting emerging IP companies I have come across is Credo (meaning “I believe”). Credo delivers high-performance, mixed-signal semiconductor IP including SerDes and interconnect products for 25G, 50G, and 100G connectivity. Walden International led Credo’s first round of funding in 2015 and if you look at the management profiles you will see deep Marvell Semiconductor experience. I did get a chance to catch up with Jeff Twombly of Credo who is quoted below. Jeff is a long time Silicon Valley semiconductor guy, very approachable, and engaging. I highly recommend getting coffee with Jeff to get the latest on the SerDes business, absolutely.

As you may know I am a big fan of the ASIC business and we have been working with Open-Silicon for the past two years on research, blogs, and we jointly published an eBook on Custom SoCs for IoT. Open-Silicon is now listed as a SiFive Company which we can discuss further in the comments section if you like. Which brings us to the recent announcement by Open-Silicon and Credo which is definitely worth a read:

SiFive, Credo and Open-Silicon Showcase End-to-End Solutions for HPC and Networking Applications at SC18 in Dallas

DALLAS, Texas – November 12, 2018 – SiFive, Credo and Open-Silicon will exhibit complete end-to-end solutions for HPC and networking applications at Supercomputing 2018 (SC18) in Dallas, TX. The co-demonstration illustrates the capabilities of SiFive’s highest performance RISC-V Core IP U7 Series, Open-Silicon’s HBM2 IP subsystem and Credo’s high performance, low power, mixed-signal 112Gbps PAM4 SerDes. Custom SoC solutions and critical IP cores, including Interlaken IP and Ethernet IP subsystems, will also be showcased.

The SiFive Core IP U7 Series is a high-performance RISC-V applications processor featuring a dual-issue superscalar core with domain-specific customizations required for embedding intelligence from the edge to the cloud. The U7 series microarchitecture optimizes performance and power enabling high throughput systems for diverse compute workloads and form-factors. Credo’s 112G SerDes, silicon proven in advanced 7nm FinFET node, enables rapid build-out of next-generation 100G, 400G and 800G Ethernet cloud networks, and delivers higher bandwidth, lower power and optimum lane count configurations. Open-Silicon’s HBM2 IP subsystem solution, in FinFET technologies, includes an HBM2 controller, PHY and interposer I/O. It provides the highest performance and flexibility for integrating HBM directly into next-generation custom SoC 2.5D SiP solutions.

“The SiFive Core IP U7 Series provides a compelling feature set that includes scalability, extensibility, 64-bit architectures, and a heterogenous coherent combination of real-time and application processors for next generation compute requiring embedded intelligence,” said Jack Kang, VP of Product Marketing, SiFive.

“Credo’s silicon-proven 56G/112G SerDes IPs, combined with Open-Silicon’s SerDes Technology Center of Excellence, minimizes risk and time-to-market for developing next generation HPC and networking custom SoCs,” added Jeff Twombly, Vice President of Marketing and Business Development, Credo.

“This collaborative demonstration with SiFive and Credo is an excellent opportunity to unveil the power of a complete end-to-end solution for next generation custom SoC solutions for high-performance and bandwidth applications,” said Shafy Eltoukhy, SVP of Operations and GM, Open-Silicon.

About SiFive
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. www.sifive.com

About Credo
Credo is a leading provider of advanced SerDes IP. www.credosemi.com

About Open-Silicon

Open-Silicon, a SiFive company, is a system-optimized custom SoC solution provider. www.open-silicon.com

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