I first got involved with layout generators back in 1982 while at Intel, and about 10% of a GPU was automatically generated using some code that I wrote. It was an easy task for one engineer to complete, because the circuits were digital, and no optimization was required. In an IEEE paper from the 2022 18th International Conference… Read More
Electronic Design Automation
Hazard Detection Using Petri Nets. Innovation in Verification
Modeling and verifying asynchronous systems is a constant challenge. Petri net models may provide an answer. Paul Cunningham (GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.
The
… Read MoreEDA Product Mix Changes as Hardware-Assisted Verification Gains Momentum
The Design Automation Conference, as always, is a good barometer on the state of EDA and my area of interest, verification. The recent DAC offered plenty of opportunities to check on trends and the status quo.
Remarkably, exhibitors and attendees were upbeat about the chip design landscape despite concerns about supply chain … Read More
WEBINAR: A Revolution in Prototyping and Emulation
This webinar will introduce to you a revolutionary new way to do prototyping and emulation at best-in-class performance, productivity, and pricing by unifying the hardware and a new software stack so one system is capable of prototyping and delivering essential emulation functionality.
Register Here
The speed of Moore’s law… Read More
An EDA AI Master Class by Synopsys CEO Aart de Geus
I consider Dr. Aart de Geus one of the founding fathers of EDA and one of the most interesting people in the semiconductor industry. So it is not a surprise that Aart was chosen to attend the CHIPs Act signing at the White House.
Here is his current corporate bio:
Since co-founding Synopsys in 1986, Dr. Aart de Geus has expanded Synopsys… Read More
UVM Polymorphism is Your Friend
Rich Edelman of Siemens EDA recently released a paper on this topic. I’ve known Rich since our days together back in National Semi. And I’ve always been impressed by his ability to make a complex topic more understandable to us lesser mortals. He tackles a tough one in this paper – a complex concept (polymorphism) in a complex domain… Read More
Delivering 3D IC Innovations Faster
3D IC technology development started many years ago well before the slowing down of Moore’s law benefits became a topic of discussion. The technology was originally leveraged for stacking functional blocks with high-bandwidth buses between them. Memory manufacturers and other IDMs were the ones to typically leverage this … Read More
ARC Processor Summit 2022 Your embedded edge starts here!
As embedded systems continue to become more complex and integrate greater functionality, SoC developers are faced with the challenge of developing more powerful, yet more energy-efficient devices. The processors used in these embedded applications must be efficient to deliver high levels of performance within limited power… Read More
Digital Twins Simplify System Analysis
The ability to digitally replicate physical systems has been used to model hardware operations for many years, and more recently, digital twining technology has been applied to electronic systems to better simulate and troubleshoot the systems. As explained by Bryan Ramirez, Director of Industries, Solutions & Ecosystems,… Read More
Understanding Sheath Behavior Key to Plasma Etch
Readers of SemiWiki will be well aware of the challenges the industry has faced in photolithography in moving to new nodes, which drove the development of new EUV light sources as well as new masking techniques. Plasma etching is another key step in chip manufacturing that has also seen new challenges in the development of new sub-10nm… Read More


ASML and TSMC’s 12-Inch Photomask Initiative: Technical Significance