S2C Targets Faster RISC-V Bring-Up With Prototyping and AI

S2C showcased FPGA prototyping and AI-assisted debugging at the sixth RISC-V Summit China, outlining how developers can validate complex processor designs and begin software development before first silicon. Its demonstrations connected three stages of that effort: running substantial RISC-V systems on FPGA hardware, automating initial RTL compilation analysis, and using large language models to help interpret virtual-platform debug data.

Held October 18–20 at the Shenzhen Convention and Exhibition Center in Futian, the summit brought together processor architects, IP suppliers, EDA providers, and software developers. Discussions covered artificial intelligence, high-performance computing, software enablement, and chip design and verification, reflecting the increasingly broad engineering demands surrounding RISC-V adoption.

At its booth, S2C demonstrated an Andes Technology AX66-based RISC-V configuration running Linux KVM on its Prodigy S8-100 FPGA prototyping system. The design used 55% of the resources available on a single AMD Versal Premium VP1902 FPGA.

That utilization figure provides a concrete indication of the platform’s capacity for multicore, 64-bit RISC-V IP prototyping. It also shows why FPGA capacity matters beyond fitting a processor core: developers need room to evaluate system behavior and exercise software in a representative environment. S2C positioned the demonstration around early software validation, including evaluation of edge AI inference workloads.

Running Linux KVM adds another dimension to that validation. A virtualization environment brings interactions between operating-system software and processor capabilities into the development process before manufactured chips are available. However, the demonstration and resource-utilization figure should not be read as measurements of final silicon performance or application throughput.

S2C also demonstrated RCF Agent using RTL from the open-source XiangShan RISC-V processor. The agent starts compilation, gathers error messages, and generates an initial analysis, automating repetitive work that engineers otherwise perform while preparing a large design for further development.

The significance is practical. Before teams can investigate deeper functional issues, they must establish a working compilation flow and understand failures. Automating the first pass can make triage more efficient and reduce the effort needed to begin working with unfamiliar RTL. The demonstration concerned initial analysis; it did not establish that the agent independently resolves every error or replaces engineering review.

In the summit’s chip design and verification forum, S2C presented “LLM-based RISC-V Virtual Platform & Debug Flow.” The presentation addressed a broader problem: as systems become more complex, failures can involve instruction execution, privilege modes, memory, interrupts, peripherals, and software simultaneously.

Traditional investigations require engineers to correlate logs, register values, memory dumps, and disassembly manually. That process can consume substantial time, while incomplete records make failures difficult to reproduce or transfer between colleagues.

S2C’s proposed workflow combines a virtual platform modeling the processor, memory, buses, interrupt controller, and common peripherals with an LLM-assisted layer that interprets captured debug information. The platform can boot firmware, bootloaders, and operating systems, and supports breakpoints, watchpoints, state inspection, and execution tracing.

Saving and restoring execution state is particularly relevant to collaborative debugging. It gives teams a repeatable starting point for examining failures, comparing outcomes, and testing explanations. The LLM layer could help organize and interpret evidence, while engineers remain responsible for validating conclusions against the underlying execution data.

Bottom line: RISC-V development increasingly depends on coordinating hardware verification with software readiness. FPGA prototypes, compilation automation, and reproducible virtual-platform investigations address different sources of delay in that process. Together, they offer a route toward discovering integration problems earlier, when teams still have opportunities to change the design before fabrication.

Also Read:

Design the Right Chip: Why Prototyping Has to Be Easy

S2C Prodigy Complete Prototyping Solutions—and Why They Matter

Shift Left with S2C Prodigy: From RTL Verification to Real-World Software Validation