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Learning on the Edge Investment Thesis

Learning on the Edge Investment Thesis
by Jim Hogan on 05-20-2019 at 5:00 am
Categories: EDA, RISC-V, Synopsys, TSMC
2 Comments

It is said that it will cost as much as $600M to develop a 5nm chip. At that price, only a few companies can afford to play, and with that amount of cash in, innovation is severely limited.

At the same time, there is a stampede in the artificial intelligence (AI) market where around 60 startups have appeared, many of which have already raised $60M or more. $12B was raised for AI startups in 2017 and, according to International Data Corporation (IDC), is expected to grow to $57B by 2021. Most of these are going after the data center, which is necessary to get the required ROI when you have a big raise. The chance of success is slim, and the risks are high. There is an alternative for investors and startups.

In this investment thesis, I talk about large disruptive changes happening in the semiconductor industry and the opportunities this creates for innovative architectures and business models.

I used a specific startup – Xceler, who are taking an alternative route to the development of an AI processor. A second organization – Silicon Catalyst is enabling them to bring silicon to market with much lower cost and risk. In the interest of full disclosure, I am a director and investor of both Xceler and Silicon Catalyst.

I love getting feedback and I share that feedback with people, so please let me know what you think. Thanks – Jim


Fig 1. Costs associated with SoC development at each manufacturing node. Source: IBS

Success with semiconductor investment in general, and AI specifically, is a multi-step process. At each stage, the goal is to reduce risk and maximize the potential for success at the lowest possible cost in dollars and time.

The low-risk structured approach comes down to executing the following steps:

  • The requirements in the chosen markets are distilled into the minimum functionality required, and target architectures identified.
  • The solutions are prototyped using FPGAs and proven in the market, creating initial revenue.

With these two steps, you have proof of technology proficiency and early market validation.

  • The solutions are then retargeted to silicon, adding further architectural innovations. An important element of this step is the utilization of silicon incubators that significantly reduce cost and risk. For an AI semiconductor startup, aside for people costs, significant costs are EDA tools and silicon. Typically, this is in the range of $3 to $5M. If the company can avoid or reduce that expense, they will see a much higher enterprise valuation and retain more ownership for the founders and early investors.

Identify the Market Opportunity


Source: AI Insight, August 30th, 2018

The AI/ML market in the data center is large. For a lot of applications, data collected at various nodes will move back to the data center. These are the public clouds such as those run by large data center companies. The problem for a semiconductor company, or sub-system vendor, is the business model associated with AI/ML in the datacenter. Systems and semiconductor companies build hardware and tools that are powerful and can run a multitude of applications, but the question is what type of AI/ML and what specific applications? It is a solution looking for a market. You need something that people would want to use.

The Cloud provides the infrastructure that your accelerator is integrated into, and they sell repeated services/applications on top of it until the product reaches the end of life. That is not a sustainable business for the technology provider. You can only sell so many units and you can’t keep selling the same volume every year. Consider how NVIDIA’s GP/GPU sales are tapering off. Sales are typically tied to the silicon cycle where every few years more silicon at a lower price, lower power consumption and improved performance becomes available. The services to get customers on board are offered for free, which is the best price, or for cheap, as the service provider is relying on volume sales with a lot of customers/users. This drives the commoditization of the underlying infrastructure as the service providers want the infrastructure at a price that makes business sense for them. In addition, with the slowing of Moore’s law, this forced obsolescence of technology is no longer a driving factor.

The ideal target is a problem looking for a solution, and for Xceler, it was found in the industrial space. Everybody wants to deploy IIoT (Industrial IoT with AI/ML), but each company is looking for the right solution. Consumer IoT was considered but most of the solutions are nice or cool to have, as opposed to must-have. In the consumer space, there are multiple policy hurdles such as legal, privacy, security, or liability. The adoption of these solutions requires a socio-economic behavioral change in the consumer mindset. It is something that requires a generational adoption cycle and a lot of marketing/PR dollars. Conversely, the adoption of industrial solutions is faster because it is a must-have capability that directly affects their bottom line.

Even though the IIoT market is fragmented, fragmentation can be your friend. Each of the larger companies in this space has a top line revenue of $50 billion per year plus. Even with limited market penetration, it is possible to build a sizeable revenue base. There are many potential end-customers, collectively presenting an opportunity, unlike the data center space where there are only a few end customers.

Predictive training and learning on the edge – the dream is now a reality with AI.
Web-based solutions appear to be free. However, someone is paying for the services. In the case of the web, it is advertisers or people trying to sell products. In the industrial space, suppliers are selling both the hardware and the solution. They are directly providing value to the purchaser and can thus make money from that directly, plus there is the potential for future revenue as more capabilities are added.

Every edge-based application is different. This fragmentation is one reason why people are scared of the edge market. You must have the ability to personalize and adapt to the context in which you are deployed. That requires learning on the edge. Inferencing is not enough. If the link breaks, what do you do? Solutions that only perform inferencing could endanger lives.

Some people are trying to build edge-based platforms. These often contain custom edge-based processors for a specific vertical application. They have the characteristics of very high volume but relatively low average selling price in comparison to Cloud devices.

I asked the founder and CEO of Xceler, Gautam Kavipurapu, about his company’s experience in the development of an edge-based processor and application. “We are running a pilot program for a company that makes large gas turbines. They are instrumented in many ways. Fuel valves have flow controls, sensors record vibration and sound, rotation speed at different stages of the turbine is measured, combustion chamber temperature – about 1000 sensors in total. We process the data and do predictive maintenance analysis.”

When the processor is connected to the machine and without connectivity to the Cloud, which may not exist for security reasons, the profile for the normally functioning system is observed. It builds a basic model for the machine, and over time, that model is refined. When you get deviations, the data from the sensors is cross-correlated in real time to figure out what is causing the anomaly. A connection to the Cloud enables the heavy lifting to build a refined model and make micro-refinements to it. However, there are huge advantages in doing the initial processing at the edge in terms of latency and power.

Define the Right Architecture
Systems need to be architected for the problems that they are solving. “We look at problems as hard real-time, near real-time or user time,” explains Kavipurapu. “Hard real-time requires response times of 5 microseconds or less; near real-time requires response times within a few milliseconds, and lastly, user time can take hundreds of milliseconds or minutes. Consumer applications fall within the last category and usually do not have Software License Agreements (SLAs)[BB2] [BB3] and performance commitments so they can work in concert with the Cloud. For problems that require hard or near real-time responses, relying on the Cloud is not viable as the round-trip time itself will take several milliseconds if it manages to complete at all.

“We have seen edge-processors evolve over time. Initially, machine learning on the edge meant collecting data and moving it to the cloud. Both the learning and inferencing were done in the Cloud. The next stage of advancement enabled some inferencing to be done on the edge, but the data and the model remain in the Cloud. Today, we need to move some of the learning to the edge, especially when real-time constraints exist, or you have concerns about security.”

Prototype and Create Revenue Stream
For this class of problem, it is possible to prototype it in an FPGA. For applications that do not need blistering performance, you can even go to market in the seed round with this solution. This offsets the need for more investment dollars and enables the concept to be validated.

“With Xceler, we started with an FPGA solution. They are acceptable in the market place we are targeting since they have good price/performance and power numbers. They are comparable to x86-based systems in price points and provide higher performance. The only downsides are that the margins are compressed, and certain architectural possibilities are not available in an FPGA solution.”

Migrate to Silicon
To capture more value, you do need a solution that is cheaper, faster and lower power. “That involves building a chip, or Edge-Based Processor (EBU),” adds Kavipurapu. “For the control processor, we are using a RISC-V implementation from SiFive. SiFive does the backend design implementation, reducing the risk for us. SiFive is also a Silicon Catalyst partner. We expect our FPGA solution to translate to between 20 million to about 36 million ASIC gates and so the proposed chip does not have to be that large.”

The only risk that remains is silicon risk. By doing the chip in 28nm, a well-understood fabrication process, the manufacturing silicon risk is minimized. All that remains are closing the design and timing which is a much-reduced problem. We have taken out most of the variability in the design element. In addition, we have restrained our design approach using only simple standard cell design with no custom blocks and no esoteric attempts at power reduction.”

Refine architecture
The FPGA solution cannot run faster than about 100MHz. “With an FPGA, we are also constrained by the memory architecture,” explains Kavipurapu. “For the custom chip, we are deploying a superior memory sub-system. New processing techniques require memory for data movement and storage. For us, to execute each computation, it takes about 15 instructions on an FPGA, which will be reduced to 4 or 5 on the ASIC. In terms of clock frequency, we will be running at 500 MHz to 1 GHz in an ASIC at a much-reduced power.”

Usage of silicon incubator
The goal of Silicon Catalyst is to limit the friction for getting an IC startup to the point they can secure an institutional Series A round by reducing the barriers to innovation. This has provided Xceler with a significant advantage compared to potential competition. While the competition struggles with multiple tape outs to achieve working silicon, burning through their dollars before first revenue, Xceler had first revenue even before the tape out. This happened because of the lower risk strategy and help from Silicon Catalyst and others.

“Silicon Catalyst offers through in-kind contributions from ecosystem partners capabilities for startups to get the tools and silicon they need,” says Kavipurapu. “It enables them to get an A round of funding that is nice in terms of valuation and raise. They bring the ability to prototype a chip at a very low cost. We get free shuttles services from TSMC. We do not have to pony up for chip design tools because there are in-kind partnerships for tools from Synopsys. We have licenses to each tool for 2 years. Silicon Catalyst also has a lot of chip industry veterans. I am not a chip guy and neither is my team. When it comes to silicon, Silicon Catalyst adds a lot of value.”

The result is that Xceler will have working samples for a little over $10M. They have customers and could be breakeven before they get to silicon.

Conclusions
We are in an era where innovation is more important than raw speed, the number of transistors or the amount of money invested. There are opportunities everywhere and getting to market with silicon no longer requires building silicon for extremely high volumes and margins. We are in the age of custom solutions designed to solve real problems and there are countless opportunities at the edge.

I’m convinced that Xceler’ s opportunity is much less risky with the help of Silicon Catalyst and the use of an open source architecture (RISC-V). I believe there will be many companies that will follow a similar path – Jim[RC5].

A Final Note
Gautam Kavipurapu was critical to me in creating this post so I’d like to tell you a bit more about him. Gautam has 20 years of experience at both large and small companies in operations, technology and management roles, including setting up and running geographically distributed teams of over 150 employees (India, US, and Europe). Gautam has 14 issued and several pending patents covering systems, networking, computer architecture. He also has several IEEE conference papers to his credit. Gautam’s team at IRIS Holdings in 2001 demonstrated a “Virtual Router,” a software router (modeled as a dataflow machine similar to Google Tensor) on a PC with NIC cards as part of the IRIS (Integrated Routing and Intelligent Switching) system development (Today’s NFV). His inventions and innovations have preceded major technology to various companies in the storage and computing industry worldwide for millions of dollars and cited in more than 350 issued patents. Gautam has an Executive MBA from INSEAD and a BSEE from Georgia Institute of Technology.

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Chips are the bleeding edge of China trade war Recovery

Chips are the bleeding edge of China trade war Recovery
by Robert Maire on 05-17-2019 at 7:00 am
Categories: Semiconductor Advisors, Semiconductor Services
4 Comments

Last week we warned of a further down leg due to China trade. We were surprised how quickly our prediction came true as it appears we are now in the midst of giving back all the upside built in to stocks based on a peaceful resolution of the trade conflict which obviously isn’t happening.

Many of the semi stocks we cover were down anywhere from 3% to 5% or more on Monday and had a partial bounce back on Tuesday. There is likely more downside beyond that as details of China’s retaliation come out. If the US goes tit for tat and retaliates to the retaliation its going to be a longer drop.

Chips are much more exposed than average company
We think today’s stock action was more or less a knee jerk reaction without a lot of analysis on specific names. As investors and analysts do the math, the impact on chip companies will be more than this initial reaction.

What is very difficult to calculate is the derivative impact from the many trade related issues of up stream companies from the semiconductor industry. Given that chips are used in many many applications and China is the biggest consumer of chips with many of those bound for re-export to the US, there is a lot of derivative impact.

The iPhone supply chain example
Iphones are in the cross hairs of the trade dispute given that they are made in China. It sounds like they may not escape the tariffs no matter how much the administration talks about “Tim Apple”.

The iPhone is the pinnacle of the semiconductor industry as it is driving the leading edge of Moore’s Law at TSMC which is currently the technology leader in the industry. Intel and PCs are far from the driver.

Apple has also been the biggest driver of TSMC’s conversion to EUV due to Apple’s demands and competition from Samsung. The iPhone also sucks up a huge amount of NAND memory in an industry already oversupplied despite 256GB Iphones.

Obviously all the CPU, GPU, comms chips and support chips in an iPhone add up to roughly $150 worth of chips alone in the bill of materials. Multiply that by 200 million phones a year and you get roughly $30B out of a $400B chip industry (at least).

There is zero chance of Apple moving production out of China in the next 5 to 10 years so iPhones are hostage in the trade war.

A tax not a tariff
If we assume a $1000 iPhone has a 25% “tariff” placed on it, it likely becomes a more expensive iPhone perhaps close to a $1250 iPhone. Foxconn, Apple’s manufacturer in China lives on relatively small gross margins which don’t allow it to absorb the impact of a tariff. Apple, is very concerned about anything that will hurt its margins and profitability and has already become the high end smart phone product in the market. This suggests that Apple will not absorb much of the price increase either.

The majority of the price increase will be passed on to US consumers as higher prices for iPhones. This means that Apple’s competitors, like Samsung and LG will have an even bigger price advantage as they can compete with phones made in Korea, Vietnam or elsewhere. This means that Apple will likely lose even more share to Samsung and LG (and others) in the phone market as Apple’s products will be less price competitive.

Obviously this will have the impact of less phones being sold by a US company (Apple) and more being sold by foreign competition (just not the Chinese).

So at the end of the day it becomes a “tax” on US consumers leading to less product sold by a US company with more product going to foreign competition.

Trickle down to chips and further down to chip equipment
The effect will be more like a bowling ball rolling downhill rather than a soft trickle down effect. It is highly likely that the trade war will only strengthen China’s resolve for “made in China 2025” to get out from under the US’s dominance. China could easily take a very hard line and push from the government on down to make Chinese companies use any other chips than US chips and any other equipment than US equipment.

If the Chinese didn’t get the message with ZTE, and then with Jinhua, they certainly are getting the message loud and clear now.

We think the response will be for China to double down on its “made in China 2025”. Perhaps financially helping out its chip industry even more. Buying semi equipment tools outside the US and developing more tools in China. If anything, IP could be more at risk as China needs to accelerate its independence through what ever means necessary. We don’t see China “knuckling under” in the trade war.

Downcycle lengthened?
The current chip downcycle which many were hoping might start to ease in the second half of 2019 will clearly take much longer to recover with a raging trade war. The downturn would clearly last well into 2020 and perhaps well beyond that.

When the recovery happens, the upturn will be more muted and we could see other countries, not involved in the war, benefiting and recovering first. Korea would likely gain share in both chips and equipment as would Japan.

The stocks
What we saw in the stock market on Monday and Tuesday was no more than headline risk and reaction. The downturn and partial rebound in stock prices was not based on new calculations of P/E ratios or P/S ratios calculated on lower levels of business due to the trade war. It will take several quarters of results to figure out how bad the impact would be.

We could start to see the negative impact in the June quarter with companies missing their current forecasts that they just made at the end of the March quarter as shipments get held up or stopped. Its likely that business would slow until the “tariffs” are sorted out.

There also may have been some “channel stuffing” in those sectors that could ship in front of the tariff imposition to get product across borders before tariffs changed. This could also cause a weaker June quarter. One of the main issues is that we just don’t yet know. Even if China and the US cease hostilities and bang out a deal ASAP, we will still see significant impact in the June quarter.

Right now, both sides appear to still be in escalation mode so the hopes for a resolution prior to the end of June seem weak at best. We don’t think the last two days stock action is a good predictor of where we are going, we still think the downside risk is higher than the upside risk. So far this assumption has been right given the turn of events.

A general position in the semiconductor industry may be to be long non US chip industry players such as Korea, Japan and others and generally short US chip industry especially those with high China exposure.

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IC to Systems Era

IC to Systems Era
by Daniel Nenni on 05-16-2019 at 12:00 pm
Categories: Automotive, EDA, Events, FinFET, IROC Technologies, Siemens EDA

One of my favorite EDA disruptions is the Siemens acquisition of Mentor, pure genius. Joe Sawicki now runs the Mentor IC EDA business for Siemens so we will be seeing him at more conferences and events than ever before. Joe did a very nice keynote at the recent U2U conference that I would like to talk about before we head to the 56thDAC in Las Vegas. You will see more of Joe there for sure.


Joe covered quite a bit of material over 47 slides so I will talk to my top 5:

Apple’s Domain-Specific Processor Evolution
The Apple Ax SoC progression slide. Apple started with TSMC in 2014 on the 20nm process delivering the A8 inside the iPhone 6. I bought six of them for my family and it was a great Apple experience. Apple packed about 2B transistors inside a 89mm2 die. Four years later we have the iPhone 10xs with a TSMC 7nm A12 SoC with an 83mm2 die and close to 7B transistors. Simply amazing. And one thing I can tell you that Joe cannot is that Apple could not have done it without Mentor and the rest of EDA.

Physical Design Complexity Continues
The average DRC operations and rules slide. 28/22nm context sensitivity and smart fill, 16/14nm FinFET and Double Patterning, 10/7nm cutOD and pattern matching, 5/3nm EUV + DP and SADP Opt. This right here is an example of EDA ingenuity. I cannot count how many times in my 35 year career that I heard the next process node couldn’t be done or would be too expensive (7 customers for 7nm and 5 for 5nm). Complete and utter nonsense.

3nm Node Manufacturing Technology Challenges
EUV Multi-Patterning required for achieving pattern resolution, gate all-around transistors trigger new extraction requirements and physical failure modes, PPA metrics drives accuracy of lithography process model below 0.3nm RMS, and multi-beam mask writing enables curvilinear masks for most advanced lithography. We got a more detailed look at 3nm GAA technology at the Samsung Foundry Forum this week. Tom Dillinger will write in more detail about it but Joe is right on the money here. Samsung announced PDK availability for 3nm and I can tell you that Mentor was a big part of that effort as well.

Systems Companies Growing Percent of Foundry Sales 5-Year CAGR +70%
Another significant EDA change that has evolved over the previous six years is the customer mix. Following Apple, systems companies are now taking control over their silicon destiny and developing their own chips. In 2018, according to Joe, systems companies contributed 17% to foundry sales. IDMs 16% and fabless companies 67%. Ten years ago it would have been all IDM and fabless companies.

Mentor Safe IC
The most complete functional safety IC solution automating the path to compliance: Lifecycle management, safety analysis, safety verification, design for safety. Here is my concern, when I first started in semiconductors, TVs and minicomputers were the semiconductor drivers and those products were built to last many years. The mobile era changed all that. We can reboot our phones with impunity or buy a new one just about anywhere if it stops working. Transportation related semiconductors are a different story. The average ownership for a new car is more than 10 years and you can’t reboot your semiconductor laden auto with impunity. Truly autonomous cars will require massive amounts of validation and verification (another one of Joe’s slides) before I will trust my family’s life with one.

Joe also did an overview of the Siemens software leadership and commitment to EDA. My former employer Solido was used as an example. Solido was the first EDA acquisition after Mentor became part of Siemens. I can tell you from personal experience that it was the best acquisition integration I have ever seen, absolutely.

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The IoT will meet 5G soon, but not with the old SIM cards

The IoT will meet 5G soon, but not with the old SIM cards
by Tom Simon on 05-16-2019 at 7:00 am
Categories: 5G, IoT, IP, Mobile, Synopsys

By now you have probably realized that 5G is a lot more than an incremental change from previous 3G and 4G cellular technology. For instance, 5G will be used to connect our phones in completely new ways, such as with microcells in urban areas using mm-wavelength signals. 5G will also include two low power protocols that are intended for use by IoT devices. One is Narrowband IoT (NB-IoT), which is intended for indoor use, with low power and long battery life. The other is LTE-M, which has a higher data rate and range than NB-IoT. However, it is still intended for machine to machine (M2M) links. GSA reports that as of March 2019 104 operators in 53 countries have already deployed or launched one or both of NB-IoT or LTE-M technologies.

While they may be different than the protocols used for voice handsets, NB-IoT and LTE-M will share the high security offered by SIM (subscriber identification module) technology. Many of today’s IoT devices are now living in a wild west type of security environment. Understandably, the move to a robust identification will be welcome indeed.

SIM conjures up images of those hardware modules that are inserted into our phones to enable devices to work on carrier networks. Today cell phone and mobile hot spot users need to fumble with SIM cards when it comes time to switch carriers, or devices. Inserting and removing SIM cards might be fine for the devices we keep on our person, but IoT deployments often consist of many devices, which might be far flung and/or difficult to access. Simply put, swapping SIM cards is a non-starter for IoT deployments in the future.

A SIM card is not just a machine-readable serial number. It’s an application running on a processor and storage in the card itself. The physical card is called a Universal Integrated Circuit Card (UICC). The UICC has storage for user specific information such as a phone book and text messages, in addition to the unique identifier for the wireless customer. Because the UICC is self-contained, it can be securely manufactured to ensure security. In order to replace the SIM card with something embedded in the connected device, remote provisioning protocols were developed by the GSMA. This new embedded UICC is called eSIM or eUICC and is frequently a small chip that is soldered into the IoT or mobile device when it is manufactured. However, this still adds to the BOM, requires extra steps in manufacturing and takes up precious space in the device.

The next step in this evolution is a fully integrated UICC, called iSIM, that can be designed right into the device’s SOC. Extra care must be taken to provide a secure execution environment for the iSIM. Synopsys has recently published a write up on their website that goes into the topic of putting together a complete solution for iSIM, including hardware IP, application software and remote provisioning capability. iSIMs can be used with any service provider, but there is still a need for a commercial solution to transfer Profiles for any carrier into the iSIM. Synopsys has partnered with Truphone for this service and has completely integrated the process to eliminate boot strap issues in the field.

Designers can start with Synopsys DesignWare tRoot Fx Hardware Secure Modules (HSMs) and add their own preferred eSIM/eUICC solution, which could be from an internal source, a Synopsys partner or any third party. The Synopsys HSM contains all the hardware modules needed to build a secure working iSIM. Alternatively, Synopsys offers the tRoot V330 HSM for iSIM that is a complete solution.

Reference: Move the IoT from WiFi to Global Cellular – Securely

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56thDAC ClioSoft Excitement

56thDAC ClioSoft Excitement
by Daniel Nenni on 05-15-2019 at 12:00 pm
Categories: Cliosoft, EDA, Events

As the number one 56thDAC supporting portal we will publish what’s happening in the conference, on the exhibit floor, and outside activities. The SemiWiki bloggers will be out in full force with live coverage and behind the scenes looks. Remember, SemiWiki bloggers are actual semiconductor professionals with hundreds of years of combined experience. There is no media team out there that loves DAC more than we do, absolutely.

ClioSoft is also a longtime DAC and SemiWiki supporter and let me tell you ClioSoft CEO Srinath Anantharaman does not spare the DAC expense:

ClioSoft DAC Demo Description

Join us at the 56th Design Automation Conference (DAC) in Las Vegas, NV in booth #927 to learn about our industry standard SoC design and IP management solutions that are tailormade for the semiconductor industry.

 

  • SOS7 platform is the design collaboration system of choice for analog, RF, digital and mixed-signal designs at over 300 companies such as Analog Devices, arm, Cadence, Google, Mediatek and TSMC.
  • designHUB platform, launched two years ago, successfully enables companies in making IP reuse a reality within their enterprise.


Re-using Your IPs To Develop SoCs Faster

  • What internal or 3[SUP]rd[/SUP] party IPs are available for use within the company?
  • How can I search and compare IPs, review their usage and resolve any questions with the IP developers prior to selecting the IP?
  • Can I review the experience of other designers using this IP before using it?
  • How can I track and prevent the unauthorized usage of 3[SUP]rd[/SUP] party IPs?

The designHUB platform empowers you to easily search for IPs across your company, compare the results, review their issues across hierarchies, qualify and select the desired IP for your project. Collaborate with your fellow team members and keep them in-sync during the development phase of your SoC and leverage the existing IP knowledgebase to resolve any IP issues in a timely manner. On completion, publish your SoC or parts of it into the IP repository with the desired access controls. In this demo, you can learn how to track the IPs and their usage throughout your enterprise, set up checks to prevent IP theft and leverage a live and growing knowledge-base for better efficiency.

Managing And Reusing Your Analog IPs Successfully

  • Do you want to browse for IPs from the Cadence Virtuoso platform based on certain criteria such as libraries, process nodes, foundries etc.?
  • Do you want to download a version of an IP into your workspace, make the necessary modifications and publish it, directly from Cadence Virtuoso?
  • Do you want to track the usage of the analog IPs and its variations throughout the company?
  • Do you want receive notifications on changes made to the IPs used in your project?

This demo will explain how to collaborate easily with different teams to develop and publish your analog IPs directly from the Cadence Virtuoso platform by using the designHUB ecosystem. You will learn how to create, manage and reuse the different versions of IPs for specific PDKs and foundries by using the designHUB platform while leveraging a live and growing knowledge base. See how your team can collaborate efficiently on their analog/mixed signal designs and leverage internally developed resources – semiconductor IPs, flows, scripts etc. to build SoCs successfully within a shorter time.

Managing Your Designs For Successful Tapeouts

  • Are you struggling with managing design data from multiple design flows across multiple design centers?
  • Do you find it difficult to manage design handoffs between teams of your project?
  • Are you spending too much time investigating changes made to the design or wondering whether you have the latest version of the design data?
  • Are you blowing up your budget on network storage?

Learn how you can leverage the SOS7 design management platform, already in use by over 300 customers, for collaborating on all analog, RF, digital and mixed-signal designs, to increase their designer productivity and team efficiency. See how SOS7 enables you to manage your designs, track open issues, take snapshots of your design database and provides a non-intrusive way to manage your design handoffs between different teams. Take a look at the different ways SOS7 can keep your data secure and minimize your network storage space used for your project.

Managing Design Traceability For Automotive Electronics

  • Are you looking to identify the design modifications made since yesterday?
  • Do you want to track what design changes were made to fix this bug?
  • Do you want to trace the usage of this IP across your company?
  • Which designs have been implemented using this version of the specification?

Want to learn how you can track documents, IPs, issues and their fixes against the IP/SoC implementation? This is the demo for you. See how to view the open issues hierarchically for the IPs, be notified about the fixes, review what changed and track the usage across different SoC implementations. From a design module perspective, see how you can track the usage across different projects and view open issues associated with it or track the various documents and its revisions used during the implementation as well as the issues found against a requirement.

Visual Design Diff

  • Does your design team struggle to identify modifications made to the schematic or layout by other team members?
  • Are you having problems reviewing the changes in your schematic or layout during ECOs?

Learn to use Visual Design Diff (VDD) to graphically compare different versions of a schematic or layout and to quickly highlight the differences even when the schematic is modified by a RF designer.

About designHUB:
The designHUB platform provides a collaborative IP reuse ecosystem for enterprises. With built-in analytics and collaborative tools, designHUB not only improves IP reuse by providing an easy-to-use workflow for designers to leverage their internal resources but it also enables design teams to collaborate efficiently to develop SoCs faster. Enabling designers to be more productive, designHUB tracks and collates all activities for design projects and displays the notifications and tasks assigned in an easy review dashboard.

About SOS7:
ClioSoft’s SOS7 design-management platform empowers single or multi-site design teams to collaborate efficiently on complex analog, digital, RF and mixed-signal designs from concept to GDSII within a secure design environment. Tight integration with EDA tools, and an emphasis on performance for data transfer, security and disk space optimization provides a cohesive environment that enables design teams to streamline the development of SoCs. SOS7 facilitates easy design handoffs between teams and mitigates the possibility of design re-spins.

About ClioSoft:
ClioSoft is the pioneer and leading developer of enterprise system-on-chip (SoC) design configuration and enterprise IP management solutions for the semiconductor industry. The company provides two unique platforms that enable SoC design management and IP reuse. The SOS7 platform is the only design management solution for multi-site design collaboration for all types of designs – analog, digital, RF and mixed-signal and the designHUB platform provides a collaborative IP reuse ecosystem for enterprises. ClioSoft customers include the top 20 semiconductor companies worldwide. The company is headquartered in Fremont, CA with sales offices and distributors in the United States, United Kingdom, Europe, Israel, India, China, Taiwan, Korea and Japan.

Also Read

A Brief History of IP Management

Three things you should know about designHUB!

Data Management Challenges in Physical Design

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Getting to EMC Compliance by Design

Getting to EMC Compliance by Design
by Bernard Murphy on 05-15-2019 at 7:00 am
Categories: Ansys, Inc., Automotive, EDA

At the risk of highlighting my abundant lack of expertise in the domain, I had always viewed EMC (electromagnetic compatibility) compliance and testing as one of those back-end exercises that can only be done on the real device and depends on a combination of expertise and brute-force in chip/package/module/system design (decaps, etc) to ensure a reasonable chance of passing. One site I found has some interesting stats in this area, suggesting first time pass-rates of only 50%, and rather lax enforcement in practice for non-wireless devices, indicating that getting to compliance is not trivial, nor has it been considered especially important, at least by a significant number of vendors.

However it seems this is likely to change. As devices move into much more safety critical applications, particularly in cars, expectations are rising. Not only is there likely to be a high and more strictly enforced requirement that applications (including non-wireless devices) will not interfere with other external electronics, but also testing for immunity of the device itself to external interference is becoming more sophisticated. The FCC has announced new rules requiring EMC testing to be done only by accredited labs with the resources and equipment to meet these needs, a factor which apparently is driving significant consolidation among labs to get to this new critical mass.

So, more rigorous and more expensive testing, together with more rigorous enforcement and potentially significant fines for non-compliance. In advanced technologies running at higher frequencies, more help to design for compliance will probably be welcome. ANSYS recently hosted a webinar in which Professor Nagata of Kobe University presented the work they are doing, together with Toshiba and ANSYS, to explore methods to design for and simulate for compliance while still at the design stage. Simulation is supported by the ANSYS RedHawk and HFSS among others.

They are particularly looking at effects of interference, both internal and external, in LTE subsystems, for example in V2x applications. Here, noise can come both from internal circuitry, the regular power noise as functions in the chip become active or inactive, as well as the noise from switching power domains that are common in many low-power applications today.

They attack both components of EMC – electromagnetic interference (EMI) generated by the application, and electromagnetic susceptibility (EMS) to external interference – using the ANSYS tools. I am not going to attempt to replay the level of detail Professor Nagata goes into; you can watch the webinar replay for a closer understanding. The main top-level points I saw are that:

  • They use both passive models for the chip, package and system in their response model, and active models for the ESD devices at the chip I/Os. Their comparison of simulations based on this approach with measured response curves show good correspondence, so I’m sold that the methodology is robust.
  • Analysis starts by building EMC awareness at chip design, supported by a reference PCB model. They then iterate from package design and model through IC design based on a chip power model (CPM). The EMI component of this Professor Nagata considers fairly straightforward. He says that EMS analysis is not so easy since this needs to account for non-linearity in the ESD devices in response to potentially Watts of external signal. To deal with this they use an extended CPM model to include the active (non-linear) behavior
  • One the chip model is optimized, they pass this extended CPM model over to the PCB analysis team to support their compliance modeling, again an iterative process to optimize for and effective while managed-cost solution.

Professor Nagata did note that their work is still at the research phase, but it seems quite promising already. Building EMC compliance analysis into the chip, package and system phases of design sounds like a better way to converge on successful certification against these new regulatory requirements. You can register to watch the webinar HERE.

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Achieving a Predictable SignOff in 7nm

Achieving a Predictable SignOff in 7nm
by Alex Tan on 05-14-2019 at 12:00 pm
Categories: Ansys, Inc., EDA, FinFET

Designing with advanced-nodes FinFETs such as 7nm node involves a more complex process than prior nodes. As secondary physical effects are no longer negligible, the traditional margin-based approach applied at various design abstraction levels is considered ineffective. Coupled with the increase of device counts, failing to account for all of these effects will add design risks including impact to yield and PPA (Power, Performance and Area).

Variability and Margin
Without proper analytics, the physical effects generally accounted for as variability in many forms (voltage drop, temperature, process) and its manifestations such as timing uncertainties, margin, derating, etc., pose significant challenges to the design closure. The grid complexity in 7nm designs (with power grids in the order of 10B+ nodes) has increased and the use of ultra-low voltage supply has also compressed margin and worsened variability, demanding an increase in scenario coverage to ensure voltage and timing closures.
Furthermore, the variability increase also complicates predicting true silicon behavior, which is critically needed for a successful product ramp process.

In the Ansys Webinar titled “Addressing Multiphysics Challenges in 7nm FinFET Designs”, a holistic approach in addressing these challenges was presented. It started with the understanding of how the design fits within the process space and what types of subjected scenarios that could lead to potential design risks.

Power Integrity and Thermal
At the epicenter of these challenges is power, a critical source to each device operation on the silicon. Power distribution network (PDN) integrity drives switching activities and is prone to imbalances that could induce undesired surprises such as IR drop issues. For example, poor bump and RDL design could contribute to poor on-chip device operation or even failure at silicon bring-up.

As expected, the initial objective is to identify potential hotspot localities and fix these vulnerabilities early during the design implementation cycle. Consequently, an accurate way of quantifying the interacting physics is needed. For example, the analytics tool such as Ansys’ RedHawk helps identify an IR drop caused by packaging or design activity, and provide data points for corrective remedies.

In a wider context, assessing power integrity in the design flow starts at the power planning stage, in which grid quality is analyzed through BQM (Build Quality Metrics) approach. During the subsequent block-level build and PDN optimization, multiple reliability analysis such as static/dynamic voltage drops and signal EM (EMIR) are done. Structural grid checks are then applied to locate potential issues. Given that it is easier to put out a fire on a few trees than fighting a forest fire, fixing localized design issues early helps to contain smaller problems from getting out-of-hand. For example, taking care of the outliers in the generated histogram from analytics data can reduce the number of critical issues into a manageable list.

Aside from power, thermal is also another critical factor. The heat generation, dissipation flow and thermal couplings of chip components versus any optical components in a heterogeneous 3D-IC could impact the overall chip power or performance. Localized activities and PVT conditions also influence the device aging process.

Multivariable and Predictive Signoff
The key to tackling multiphysics challenges is to infuse analytics into the existing solution such as in power integrity methodology in such as a way that it enables a predictive signoff quality. The traditional analysis flow utilizing both vector and vectorless simulation approach has challenges, as it relies on a set of correct scenarios selection. For example, many modern designs have application dependencies that may uniquely translate to different activities sequences at the core level. Therefore, to arrive at a set of vectors that provide good coverage of activities is hard.
As the impact of multiphysics interactions are eventually measured in term of performance design metric (timing), it is necessary to facilitate feeding back the various simulation generated data points into the overall design closure flow. Ansys’ Path FX platform fills the gap between SPICE level circuit simulation and static timing analysis. It provides context-aware multiphysics timing analysis and complements the mainstream design flows by retaining the performance, capacity and usability of timing analysis engine.

Path FX target use models include to complement existing STA by validating at risk paths at each design iteration, identify safe slack and add additional guardband to at-risk paths not covered by margins. It is also capable of fine-tuning the process models for better correlation with silicon and use them to further identify at-risk paths. On a 7nm testcase, it delivers an accuracy within 2% versus SPICE simulation result. Path-FX has also been integrated with RedHawk-SC to address voltage drop impact assessment on timing. With Ansys’ SeaScape architecture it enables design teams to leverage big data analytics to handle the data demands of multiphysics chip-package-board simulation and testing.

In summary, 7nm designs are subject to a more complex multi-physics environment. Successful silicon tapeout and bring up require addressing their impacts on delay variability, validating at-risk areas on silicon and proper use of safe guardband.

To view this on-demand Webinar on how Ansys multiphysics simulations can address the different forms of variability and their impact on performance, please check HERE.

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Trade war shifts electronics production

Trade war shifts electronics production
by Bill Jewell on 05-14-2019 at 7:00 am
Categories: Semiconductor Intelligence, Semiconductor Services

The U.S. is showing steady growth in electronics production. Three-month-average change versus a year ago (3/12) in March 2019 was 6.2%, the 12[SUP]th[/SUP] consecutive month of growth above 5%. China electronics production is decelerating, with March 2019 3/12 growth of 8.2%, similar to 8.3% in February. This marks the first time China electronics production growth has slowed below 10% since November 2016. The 28 countries of the European Union (EU) displayed a decline in 3/12 electronic production in December 2018 through February 2019 following volatile but mostly positive growth the prior two years.

Electronics production in key Asian countries is also a mixed picture. Taiwan now has the highest growth in the region, with March 2019 3/12 growth of 15%, the third consecutive month of double-digit growth. Taiwan has recovered from production declines in 2015 through 2017. Vietnam’s 3/12 growth slowed to 1% in April 2019 following strong growth over the last two years, hitting over 60% in December 2017. South Korea, Malaysia, Singapore and Japan are all experiencing declines in the last few months. Japan has been weak over the last year, while the other three countries had double-digit growth at some point in 2018.

What impact has the ongoing trade dispute between the U.S. and China had on electronics production? Looking at U.S. imports of electronic equipment in the first quarter of 2019 versus a year ago gives an indication of the trends. Overall U.S. imports of electronic equipment were $58.8 billion in 1Q 2019, down $2 billion or 3.4% from 1Q 2018. Imports from China were down $3.7 billion, or 11%. Imports from Mexico held steady at $10.9 billion. Vietnam has emerged as the third largest source of U.S. electronics imports, with $4.4 billion in 1Q 2019, up $2.2 billion or 95% from a year ago. Taiwan was the fourth largest source, with $2.2 billion, up 45% from a year ago. Thailand and most other countries showed a decline in U.S. electronics imports from a year ago. The steady growth of U.S. electronics production as shown above while imports have declined indicates some possible shift of electronics production back to the U.S.

Four years ago in February 2015 we at Semiconductor Intelligence wrote about the emergence of Vietnam as an electronics manufacturer. The U.S.-China trade dispute has accelerated the growth of Vietnam electronics production. Examples of the shift include:
· In April, LG Electronics announced it would cease production of smartphones in South Korea and shift manufacturing to Vietnam.
· The world’s third largest producer of televisions, China’s TCL, in February began construction of a major TV production facility in Vietnam.
· Key Tronic, a U.S.-based contract manufacturer, expects to shift some production from China to Vietnam with the opening of a new factory in Vietnam in July.

Taiwan has also benefited from the U.S. trade dispute with China. An April Bloomberg article states 40 Taiwanese companies are moving some production back to Taiwan from China, helped by incentives from the Taiwan government. These companies are investing US$6.7 billion and plan to create over 21,000 jobs.

Although the shift of electronics production from China to other Asia countries has been accelerated by the current trade dispute, the trend has been in place over the last few years. Multinational companies are moving production to Vietnam and other countries due to lower labor costs, favorable trade conditions and openness to foreign investment.

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Re Energizing Silicon Innovation

Re Energizing Silicon Innovation
by Bernard Murphy on 05-13-2019 at 12:00 pm
Categories: AI, Automotive, Events, Intrinsix, Prototyping, S2C EDA, Synopsys, TSMC
2 Comments

Hardware is roaring back into prominence in technology innovation, from advanced cars to robots, smart homes and smart cities, 5G communication and the burgeoning electronification of industry, medicine and utilities. While software continues to play a role, all of these capabilities depend fundamentally on advances in hardware and particularly novel chip solutions: in sensing, high performance and/or low power compute and communication, AI accelerators and many more functions. Yet amidst this explosive growth, the semiconductor industry has massively consolidated. Fewer and bigger companies do their part to drive innovation but are naturally more risk-averse and more inclined to evolutionary rather than revolutionary advances. Where’s all the real innovation and risk-taking going to come from in this environment?

Thirty to forty years ago, if you could make a convincing case there were plenty of VCs ready to bankroll your venture. As manufacturing costs for advanced processes grew, VCs found the comparably minor capital needs of software ventures much more attractive and steered away from silicon business plans. But designers didn’t stop having ideas or feeling the itch to start new enterprises; they were just stalled by a seemingly insurmountable barrier to entry – raising seed and Series A funding.

Everyone knew this, but Rick Lazansky wanted to do something about it. Rick is a serial entrepreneur, actively involved in the investment community. He believed the industry needed an incubator to help silicon innovators with good ideas get past this hurdle. Incubators and accelerators are not new concepts but his creation, Silicon Catalyst, makes particular allowance for the special needs of this domain. They provide a pool of seed investors, two years of design tool access, manufacturing and test, access to a wide range of advisors with lots of industry experience and access to a premium group of strategic partners looking for innovations they need. You’ll still have to raise some of your own investment to prove you have skin in the game, but the barrier is now much less daunting.

Before you quit your job, get a second mortgage on the house and tell your significant other that the family will be living with your parents if your venture doesn’t work out, remember that as with any incubator, you’re going to have to do some work to be accepted; I’ll get to that. But first some more detail on that buffet of goodies to which you’ll have access if you cross that hurdle.

Your immediate concern is probably how you manage EDA, IP and design services, MPW, packaging and test costs. Silicon Catalyst has assembled a group of 25+ in-kind partners who will provide 2 years of free or significantly-discounted access to their capabilities and services from the time your clock starts. These include Synopsys for design tools, S2C for emulation, SiFive and Silvaco for IP, TSMC MPWs for prototype manufacturing, Advantest and EAG for test, Mathworks, AWS, Instrinsix, MEMS design and foundry solutions, patent lawyers, even a CFO app – and many more. They cover pretty much everything you’re going to need to create that prototype. These partners see value in this access because they see the portfolio companies as potential new customers.

There are multiple strategic ecosystem partners, including Bosch, On Semiconductor, Soitec and TI Semiconductor; I met the Bosch representative at a recent event. Strategic partners pay close attention to the portfolio companies working in their areas of interest. Bosch knows that that interesting startups have neither bandwidth nor the nerve to approach a company of their size. By being a strategic partner, they can interact with promising ventures very early on during the screening process and react quickly if they see a fit. Others see opportunities in hot areas such as photonics where they see potential to build further demand for their technology.

Among advisors, full disclosure – I’m now an advisor, but they have some really good people too. Just a small sample includes Dave French (past CEO of Cirrus Logic and EVP at NXP), John East (past CEO of Actel Semi), Misha Burich (past CTO and VP at Altera) and Mark Ross, (ex-Cypress Semi EVP & CTO). There are 120+ advisors aligned with Silicon Catalyst, with skills ranging from globalization to manufacturing development, angel investments, MEMS – it’s all on the website.

Investors include Rick himself, Jim Hogan and many of the advisors. There are options for seed money to come from individual investors, also from an ecosystem investor group to which multiple angels can contribute. Angels particularly are attracted by the reduced risk over personal investing. In the personal approach there’s a lot of risk and a lot of work for an investor to decide where and how much they should invest. Investing together with others in in a pre-screened group of portfolio companies can look like a pretty attractive proposition. The Silicon Catalyst approach reduces risk all round – for portfolio startups, investors, in-kind and strategic partners.

Silicon Catalyst looks at opportunities from lots of domains and geographies, spanning pre-seed to post-Series-A chip startups. Existing portfolio companies are in analog-based AI, communications, ultra-low power design and others, some in Silicon Valley but also in Canada, Korea and Singapore. From their founding in 2015, they’ve connected to over 250 startups, receiving applications from Europe, India and other locations. There’s now a joint venture in Chengdu, China focused on the power semiconductor ventures and they’re exploring the possibility of another joint venture to assist startups in Israel.


So what’s the catch? Applicants are screened through a rigorous review process; historically, only one out ten makes it through to becoming a portfolio company. That’s so all those supporting individuals and organizations feel they are getting value for their investments in the domains that most interest them. Nick Kepler (COO) told me that even though selection is obviously rigorous, he wants to make sure that each applicant gets value out of the process even if they aren’t selected. Worth remembering even if you’re not sure you are ready. This could be a way to find out what you have to do to tune up your game.

Silicon Catalyst has around 20 companies in the portfolio, they raised their own investment round last year and they’re planning to get to several hundred companies in the portfolio over the next 7-10 years. As a measure of success, they already have portfolio companies who have graduated from the incubator to Series A funding.

OK, I’m obviously biased. But c’mon – when did you last see an idea this exciting for any would-be silicon entrepreneur? If you want to learn more, first click HERE. Also know that upcoming events for their ecosystem members include a Portfolio Company Update (what others call “Demo Day”) and their Semi Industry Forum, both at the end of May. And for you entrepreneurs, the deadline to apply for the Fall Screening Event is in July. Check out their website to learn about the application process.

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The Evolution of the Extension Implant Part V

The Evolution of the Extension Implant Part V
by Daniel Nenni on 05-13-2019 at 7:00 am
Categories: Events, Semiconductor Services, Threshold Systems
1 Comment

Part 4 of this series discussed how a transistor Extension could be fabricated in a planar device without using an implant operation, and is instead formed using a preferential etch followed by a selective epitaxial deposition. This final installment of the series will present the formation of an Extension in a FinFET transistor using the same etch and deposition methodology.

As in the planar case, this technique for fabricating an Extension region depends on etching out a precisely formed cavity adjacent to, and on both sides of, the transistor channel region. Also, like the planar case, this cavity etch is performed as part of the replacement Source/Drain etch that takes place prior to the epitaxial deposition of the SiGe compressive stressor. However, in the case of a FinFET, the Extension cavity is formed as part of the fin removal process.

Figure #1 illustrates PMOS and NMOS fins just prior to the Source/Drain cavity etch and the formation of the SiGe stressor crystals. The NMOS fins are coated in a protective hard mask. (Note that the PMOS fins are located in the N-Well and the NMOS fins are located in the P-Well.)


Figure #1

The process begins by etching away the PMOS fins located outside of the gate electrode. This is accomplished by first etching away the thin coating of oxide (left on the on the top of the fins after the sidewall spacer etch), and then etching away the Silicon fins using a wet etch of NH[SUB]4[/SUB]OH. Alternate etch chemistries that will also work for this task are NH[SUB]3[/SUB]OH, TMAH, KOH, NaOH, BTMH or amine-based etchants.

Once the fins are removed, the nitride spacers along the fin sidewalls will collapse and they can be easily removed from their attachment points to the Gate Electrode nitride spacer. The result of this etch is illustrated in figure #2.

 

Figure #2

Figure #2 displays the device structure after the PMOS fins have been removed. The TMAH etches preferentially into the N-Well forming the characteristic “V” shaped groove that self-limits the etch process. Perpendicular to this groove, and along the (111) plane, the TMAH etches the silicon fin more slowly and forms the Extension cavity beneath the Gate Electrode spacer. Figure #3 displays a close-up view of the Extension cavity.


Figure #3

Following the etch, a selective deposition of SiGe takes place. This operation will deposit SiGe only on the exposed silicon surfaces which restricts the deposition to the silicon in the V-shaped groove and the Extension cavity as displayed in figure #4.

Figure #4

The Gate Electrode in figure #4 has been made transparent in order to make the Extension structure visible. Figure #5 is a close up of the Extension structure that is located beneath the Gate Electrode spacer.


Figure #5

So is this technique for forming the transistor Extension actually being used?

Figure #6 displays a Transmission Electron Micrograph of an Intel 22nm PMOS FinFET gate array.

The TEM preparation of this image makes it initially difficult to understand. It is a dark-field image so the denser materials appear lighter and the view is top-down and the Gate Electrodes have been polished back to the tops of the SiGe crystals. As a result of this polish, the Gate Electrodes no longer wrap around the top of the fins but are located on either side of them. This reveals the transistor channels and the Extensions located on either side of the channels.

As the TEM illustrates, the SiGe crystals extend behind the nitride spacers and slightly into the channel region to form the transistor Extensions. Based on this evidence it would appear that the technique described in this paper has been in use for some time.

Figure #6

Forming the transistor Extensions as part of the fin removal and SiGe deposition process offers a number of important advantages. First, it is a simpler process. It eliminates all of the implant steps required of other Extension formation methodologies and their associated photo-masking operations. More importantly, it provides a robust solution for effectively forming transistor Extension regions even with the very tight Gate Electrode pitches found at the 10/7/5nm nodes.

This technique would require careful control of the fin removal etch to ensure that the Extension cavity is formed to the correct dimensions, but the advantages provided by this method far outweigh any disadvantages.

This content was authored by Jerry Healey of Threshold Systems Inc. For detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

Also read: The Evolution of the Extension Implant Part IV