Bronco Webinar 800x100 1
Semiconductor Expert Forum

Posted on

Early IP Block Error Detection is Critical!

Early IP Block Error Detection is Critical!
by Daniel Nenni on 07-08-2019 at 10:00 am
Categories: EDA, Fractal Technologies, IP

The rising complexity of modern SoC designs, as enabled by progressing manufacturing technology, leads to an increasing validation challenge as the only way to manage complexity increase is by re-using more pre-designed IP blocks. These IP-blocks are provided by various suppliers such as a foundry partner, internal design groups, open-source IP and third-party IP companies. This is driving the trend of increasing IP Qualification costs, which is part of an exponential growth of total SoC design cost.

Cost in terms of IP qualification and design-verification is mostly found in design-time spent in verification runs and resolving the issues found. A well-known design principle is that the closer an error is detected to its point of creation, the less costly fixing it becomes. That is why design-teams deploy various techniques before accepting an IP block into their SoC design flow. Any issue found during IP qualification or incoming inspection, can be directly fixed within the IP by the IP supplier. Failing early detection, design teams are faced with the tedious path of tracing an issue in the final design back to a single IP block. After which of course the IP still needs to be repaired, re-released and re-integrated in the final design.IP qualification methods have evolved from self-certified questionnaires, through home-grown IP qualification scripting into an industry-standard IP qualification solution known as  Fractal Crossfire.

An IP qualification solution will  certify that an IP release is complete, has internal consistency and will exhibit predictable trends within and over  characterization corners. All these are must-have properties for an IP block before it can be included in any SoC design.We argue that for a design-team that is approaching tape-out, having the IP qualified is necessary, but not enough. In the scenario where a design-team is receiving regular incremental revisions of an IP block, it is also  essential that these revisions gradually converge to a steady state where changes to the IP block are limited to only  the bare minimum. If in a late stage of the design an IP block is shipped that has a large delta with respect to the   previous release, this can pose a huge risk to the final design schedule, even when the IP is successfully qualified.

Introducing IPdelta

The arrival of a new IP release close to tape-out is the high-risk scenario where IPdelta is indispensable. Anything that has ended up in this new IP release is a danger to the verification level already achieved. IPdelta will analyze the delta between the two IP revisions. Regardless of object ordering within files or databases, it will compare contents of all individual databases, models and formats and categorize the differences it finds.

Certain changes are expected — and should therefore be complete in their implementation throughout the different views. Some, or many, changes can be unexpected, indicating that the IP-release contains updates that are not necessarily needed for the current design and require further investigation. As the amount of changes can be huge, IPdelta offers users a sophisticated delta-browsing interface that allows users to quickly zoom in on changes that pose a real threat to timing and power closure

By comparing IP releases, IPdelta provides the confidence that only the expected updates are present in the new IP release so that insertion in the final design is safe.

Conclusion
It can be concluded that an IP qualification sign-off is a necessary but not a sufficient condition for safe insertion  of a new IP release into an existing SoC design. No matter how thorough an IP qualification tool is it is only made to  judge an IP release in isolation. When receiving a new IP release, designers need to be ensure that the delta between  versions is kept to the bare minimum necessary.

Posted on

Texas Instruments and the TTL Wars

Texas Instruments and the TTL Wars
by John East on 07-08-2019 at 8:00 am
Categories: John East
8 Comments

The “20 Questions with John East” series continues

Most people in the IC business understand very well that TTL products dominated our industry for 30 years or so.  They’ll also probably know that TI was the king of TTL. But,  if you ask those people what TTL is,   most won’t have any idea.  If you’re one of those people, rest easy.  You’re about to find out.

There were three IC companies that really mattered in the early days.  Fairchild,  Motorola,  and Texas Instruments (TI).  There were a handful of Wannabe’s as well —  National,  Signetics,  Amelco, Siliconix to name a few —  but Fairch,  Mot, and TI were the big guys. Intel had not yet arrived on the big scene.  The first standard logic family was Fairchild’s RTL.—   Resistor-Transistor Logic. — (Inputs came in through Resistors.  Outputs went out through Transistors.  They were Logic devices).  It was built using bipolar transistors as was almost everything in those days. Micrologic was the name they gave the family.  Sadly, RTL was brain dead.   Fairchild had a great head start.  The Noyce patent really worked. The Kilby patent didn’t.   But – the RTL circuit that Fairchild chose had big problems  — namely fan in,  fan out,  noise margin,  and speed.  Sadly, those pretty much captured everything that mattered in those days.  So – Fairchild switched to DTL. — Diode-Transistor Logic. —  (The inputs came in though Diodes.  The outputs went out through Transistors.  It was Logic).  DTL had been invented by others earlier.  IBM had used versions of it in their 360 series of mainframe computers.  It was a much better design than RTL.   It solved all of the RTL problems except speed. Fairchild introduced their DTL family in 1964.

TECHNO-BABBLE ALERT.  If you’re not a circuit geek, skip the next paragraph!!

DTL gates included back to back diodes.  The cathode of one diode (called the input diode) went to the input pad and the cathode of the other diode (called the level setting diode) went to the base of a transistor that we called the phase splitter.  The diode anodes were common.  Why not put those two diodes in the same isolation region?  Instead of two diodes, use a single bipolar NPN transistor!  The input diode would be the emitter-base junction of the transistor.  The level setting diode would be the collector – base junction of the transistor.  (for a two input gate, the transistor would have two emitters.  For a four input gate,  it would have 4 emitters.  That schematic diagram looks a little weird,  but it’s no problem to make) Why was that better?  When the input pad went low, the transistor turned on and yanked the charge off of the base of the phase splitter.  That shortened the time required to turn off the phase splitter which was the number one problem facing the engineers who were trying to speed up the circuits. As with most inventions,  it isn’t always completely clear who deserves the credit.  A real, working IC version of a TTL gate had a lot more to it than my simplified description above.  Tom Longo, working at Sylvania,  was the first to put it all together into a commercially successful IC.

It was a big breakthrough!! After working through a few “pet” names (Longo called it  SUHL and James Buie of TRW called his version TCTL), it ended up being called TTL (Transistor – Transistor Logic).  Whatever you called it, TTL was better!  It was faster than DTL with similar costs. Longo and a few others may have invented TTL, but it was Texas Instruments who made hay with it.  TI introduced their 5400  TTL family in 1964  — the same year Fairchild announced their DTL family.  But TTL was better!  TI soon put their TTL products in an inexpensive plastic package which they had developed.  The plastic package gave them lower costs than anyone else.   Early on TI sold TTL gates for $1.00 (actually twenty five cents per gate for the quad, two input NAND gate. There were four gates in each package).  That was an outrageously low price for the times.  They stole the march.  TTL took over the world and TI became the king of that world.

Why didn’t Longo et al get the credit they deserved?  TI took such a huge, early lead in TTL that everybody thought it was a TI invention.  It wasn’t.  TI recognized a good thing when they saw it and they jumped on it.  They pounded the market with it.  There’s a Harvard case study wrapped up in this somewhere.

And Tom Longo?  He later moved to Transitron and then to Fairchild.  He was a very smart guy and a butt kicker extraordinaire!  I couldn’t decide if that was a good thing or a bad thing.  I worked several levels below him at Fairchild so I didn’t interface with him on a daily basis.  The butt-kicking was sort of fun to watch  — unless it was your butt being kicked.  (Of course,  now and then I took my turn.) Speaking of butt-kicking, though, Tom never liked the fact that TI was kicking our butts with the product that he had invented.

Fairchild,  seeing the success that TTL was experiencing, later tried to get into the TTL market  — at first by introducing a proprietary family of  TTL products ( the 9000 family) instead of by second sourcing the 5400 family.   But there was a problem:  we didn’t really understand collector – emitter leakage.  (Iceo).  One thing we knew about Iceo,  though, was we had plenty of it!  Iceo was our dominant yield problem.  This was exacerbated by gold doping.  The big problem with respect to speed those days was turning off bipolar transistors.  Turning them on was easy, but to turn them off you had to wait for all the minority carriers to exit the base region.  That took forever.  Somebody had figured out earlier that a few gold atoms in the base region would help the minority carrier lifetime problem.  We called that gold doping.  You had to gold dope in order to make the speed requirements. The problem? Gold made the Iceo problem worse.  When you gold doped, leakage went up, yields went down, and costs went up.

So  —  circa 1969 — our yields were bad and costs were high.  The solution? Some of the Motorola guys brought in by Hogan in turn imported what they thought was the Motorola process (Sadly —  it wasn’t quite) and installed it in one of the Mountain View fabs. The yield was pretty good right out of the chute so we went into production.  We didn’t do HTRB (High Temperature Reverse Bias is a simplified form of Life Testing).  There were no formal qual requirements at Fairch in those days.  We just went straight into production.  Big mistake!!!!!  We had screwed up!!!   There was an Op Life problem that we would have caught if only we’d done HTRB. Several months of our early production wafers were unreliable!  After we figured out that we had a problem, we burned in some of the units we had made but threw out the rest.  It wasn’t any fun!!  Heads rolled.  The red queen was still lurking.

Off with their heads was still operative.

Tom Longo went on to become founder and CEO of Performance Semiconductor.

Next week:  The curse of P&L management

See the entire John East series HERE.

Posted on

Banks and ATMs Under Cyber Attack

Banks and ATMs Under Cyber Attack
by Matthew Rosenquist on 07-06-2019 at 5:00 am
Categories: Security

The Silence hacking crew, mostly attributed to a group of very crafty Russian hackers, has struck again pulling-in over $3 million in cash from ATMs.

At least 3 banks have been attacked in the latest campaign, with Dutch Bangla Bank being the largest. The criminal hackers first compromised the bank’s card management infrastructure then undermined the integrity of the approval systems allowing co-conspirators to use bank ATMs to withdraw large sums of cash totaling over $3 million.

This hacking crew originated in Eastern Europe around 2016 and first started attacking financial institutions in Russia, Ukraine, and Poland before expanding into the Asia Pacific region. Banks in India, Bangladesh, and Sri Lanka are the most recent targets.

Silence is considered a top tier cyber-criminal group. Their methods are technically sophisticated and they operate with a good degree of patience. There is speculation they may have deep experience in penetration, reverse engineering, application development, and even security practices.

With custom software, effective hacking skills, and a network of money mules, this band is able to victimize banks at incredible levels. Their success in stealing large sums of cash will only promote more attacks.

Customers cannot stop such attacks. Because Silence targets the banking and ATM infrastructures, there is little the everyday user can do to protect themselves other than bank with a reputable institution that will actively work to prevent, detect, and respond to such attacks.

From a risk perspective, Silence is ranking high among hacking groups. A new breed of highly capable and technically savvy threat groups are emerging. Some are direct appendages or supported by Nation States while others are smart organized criminals looking to leverage the opportunities in the digital world for their own profit. Regardless, these groups are at the forefront of developing stealthy and effective exploits, driving malware capability evolution, and pulling off some of the biggest heists against the financial community. Success allows for reinvestment in tool, capabilities, and reach. This makes them stronger and more difficult for cross-border authorities to track and take-down those responsible.

This is not the last we have heard from Silence or others of their ilk. I predict by the end of 2019 we will see a number of significant breaches to APAC banks which will stir great concern across the global financial landscape, effecting both traditional banking as well as emerging cryptocurrency exchanges.

The cybersecurity firm Group-IB has been tracking the activities of the Silence group for several years and has a good write-up of their profile and evolving techniques.

Posted on

Chapter 1 – Predicting Trends in the Semiconductor Industry

Chapter 1 – Predicting Trends in the Semiconductor Industry
by Wally Rhines on 07-05-2019 at 6:00 am
Categories: Wally Rhines
9 Comments

Figure 1 is the most basic of all the predictable parameters of the semiconductor industry, even more so than Moore’s Law.  It is the learning curve for the transistor.  Since 1954, the revenue per transistor (and presumably the cost per transistor, if we had the data from the manufacturers) has followed a highly predictable learning curve.  Before Moore’s Law, the learning curve provided a guiding light for the semiconductor industry.  Texas Instruments used it for strategic advantage and shared its data with Boston Consulting Group who published a book called “Perspectives on Experience”1.  In the days of germanium and silicon discrete transistors, companies like TI could use the learning curve, for example, to predict what the unit cost would be after 100,000 units were produced, based upon the actual cost per unit of the first 1,000 units produced.  They could then price the particular transistor product at a loss initially to gain leading market share and therefore achieve higher profitability and market influence when they reached future high unit volume sales.  TI didn’t create the technology of learning curves.  It was developed in 18852 and has been used in industries like aviation, even before the transistor was invented, to predict the future cost per airplane when a certain cumulative unit volume was achieved.  TI’s unique approach for semiconductors lay in the use of the learning curve to drive a

pricing strategy early in the life of a new component.

Figure 1.  Learning curve for the transistor from 1954 to 2019

Figure 2 shows how the learning curve works.  The vertical axis is the logarithm of the cost per unit of anything that is produced.  The product can be a good or service; anything that benefits from the experience of doing the same thing, or making the same product, again and again.  Published learning curves typically use the revenue per unit because companies are unwilling to divulge their cost data.  The companies, however, know their costs and, over the history of the semiconductor industry, have used that data to strategically position themselves against competition.  The horizontal axis of the learning curve is the logarithm of the cumulative number of units of a product or service that have been produced throughout history. When the data is plotted, it results in a straight line with a downward slope.  Cost per unit decreases monotonically as we develop more experience, or “learning”.  Since the learning curve is a “log/log” graph, the data generates a line rapidly initially as the small number of cumulative units doubles in a short period of time.  As time goes on, movement of the straight line to the right slows since it takes longer to double the total cumulative number of units.  Every time the cumulative number of units produced doubles, the line reflects a decrease in the cost per unit by a fixed percentage.  The percentage is different for different products but tends to be similar across a broad range of products in an industry like semiconductors.

Figure 2.  The learning curve is a log/log plot of cost per unit vs cumulative units manufactured

More broadly, learning curves can be applied to any good or service where the cost per unit of production can be measured. We are just not as aware of the phenomenon today because the measurement applies only when cost is measured in constant currency.  A deflator must therefore be applied to the cost numbers to account for the portion of inflation that is caused by governmentally driven inflation.  In addition, the learning curve only applies in free markets. Tariffs, trade barriers, taxes and other costs must be removed before actual cost comparisons can be made.  The reason that learning curves have been so valuable in the semiconductor industry is that it is one of the few industries that has operated for over sixty years in a relatively free worldwide market, with minimal regulation and tariffs as well as a very low cost of freight between regions.

One of the great things about semiconductor learning curves is that they will be applicable as long as transistors, or equivalent switches, are produced. While Moore’s Law is quickly becoming obsolete, the learning curve will never be.  What will happen, however, is that the cumulative number of transistors produced will stop moving so quickly to the right on the logarithmic scale.  Then the prices will not decrease as rapidly as they have in the past. The visible effect of improved learning will diminish.  At some point, monetary inflation will be larger than the manufacturing cost reduction and transistor unit prices may actually increase with time in absolute dollars even though they are decreasing in constant currency. In the meantime, the learning curve is a useful guidepost for predicting the future. Currently, in 2019, the revenue per transistor is decreasing about 32% per year.

Those who purchase microprocessor or “system on chip” (SoC) components may recognize that, in 2017, the price per transistor is decreasing at a slower rate than 32% per year. Figure 3 explains this. The 32% number applies to the total of all semiconductor components produced in 2017. However the cost per transistor is made up of different kinds of semiconductor components — memory, logic, analog, etc.  It becomes apparent from Figure 3 that the semiconductor industry is producing far more transistors in discrete memory components, particularly NAND FLASH nonvolatile memories, than in other types of semiconductors.  When the memory learning curve (consisting mostly of NAND FLASH and DRAM) is separated from the non-memory learning curve, it is evident that cost per transistor and cumulative unit volume for memory are way ahead of non-memory.  That’s okay because the learning curve doesn’t specify how the decreasing cost per transistor is achieved – only that it will happen as a function of cumulative transistors produced.

Figure 3.  Cumulative unit volume of transistors used in memory components is increasing much faster than unit volume of transistors in other types of chips.

Another aspect of interest in Figure 3 is the set of data points near the end of the curve that were generated by data from 2017 and 2018.  The data points are above the learning curve trend line. How can this happen if the learning curve is a true law of nature?  Very simply, the period from 2016 through 2018 was one of memory shortages, particularly DRAM.  Prices per transistor increased instead of decreasing because market demand exceeded supply.  Won’t this cause a long- term deviation from the learning curve?  No.  Whenever a market supply/demand imbalance occurs, the cost per transistor moves above or below the long-term trend line of the learning curve.  This is always a temporary move.  When supply and demand come back in balance, the cost per transistor will move to the other side of the learning curve.  Area generated above the learning curve will normally be compensated by a nearly equal area below the learning curve and vice versa.  This is another useful benefit of the learning curve because it allows us to predict the general trend of future prices even when short term market forces cause a perturbation.

While I’ve focused on transistors in this discussion of learning curves, it should be noted that we could just as easily use electrical “switches” as our unit of measure.  The same learning curve would then work for mechanical switches, vacuum tubes and transistors as seen in Figure 5 of Chapter 3.  This figure also shows another attribute of the learning curve.  In this case, the metric on the vertical axis is revenue per MIP (or millions of computer instructions per second) for various types of electrical switches.  Learning curves can be used to predict improvements in performance, reliability (in FITS), power dissipation and many other parameters that benefit from the cumulative unit volume of production experience.

Learning curves also provide a useful tool for predicting “tipping points” for new technology adoption.  A good example is the introduction of “compression technology” in the semiconductor test industry in 2001.  In hindsight, a major innovation like this was inevitable just by examining the learning curve for the cost of testing a transistor in an integrated circuit (Figure 4). The ATE cost learning curve was not parallel to the silicon transistor learning curve and had a less steep slope.  Industry ATE cost was not decreasing fast enough.

The ATE industry should have seen that change was inevitable.  Pat Gelsinger, in his Design Automation Conference Keynote address in 1999 highlighted his prediction that “in the future, it may cost more to test a transistor than to manufacture it”.  Such a prediction would have occurred had it not been for compression technology (also called “embedded deterministic test”) which started out in 2001 with a 10X improvement in the number of “test vectors” required to achieve the same level of test and then progressed to nearly 1000X by 20183.

Figure 4.  Until 2001, reduction in the revenue per transistor of the automated test equipment industry was decreasing at a slower rate than the transistors produced by their customers, the semiconductor component industry.

Introduction of “embedded deterministic test”, or test compression, in 2001 significantly reduced the number of testers required and, by 2012, reduced the revenue of the ATE industry by $25B per year.

 

1 Boston Consulting Group, “Perspectives on Experience”, 1970, Boston, MA

2 https://en.wikipedia.org/wiki/Learning_curve#In_machine_learning

3Rajski, J., Tyszer, J., Kassab, M. and Mukherjee, N., “Embedded Deterministic Test”, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems ( Volume: 23 , Issue: 5 , May 2004

Read the completed series

Posted on

Where Have You Gone, Lee Iacocca

Where Have You Gone, Lee Iacocca
by Roger C. Lanctot on 07-04-2019 at 8:00 am
Categories: Automotive
3 Comments

The automotive industry is a funny business. It is simultaneously ruled by ego driven “visionaries” and penny-pinching bean counters. (Don’t believe me? Just ask Bob Lutz.) This id-superego tension plays out in business section headlines every day most recently including the death of FCA’s Sergio Marchione who passed nearly a year ago and today’s news of the demise of legendary Chrysler Chairman Lee Iacocca.

At a time when two former CEOs, Martin Winterkorn of Volkswagen and Carlos Ghosn of Renault-Nissan, are facing criminal charges, it’s worth considering the absence of product-focused industry leadership from the C-level of most car companies. General Motors’ CEO Mary Barra’s brief pre-CEO flirtation with maverick behavior (“No more crappy cars!”) evaporated after her appointment and the resulting shift in emphasis to financial concerns.

Today’s CEO’s are universally focused on financial issues and meeting or battling regulatory requirements while the actual engagement with consumer desires and the marketplace is left to the marketing and advertising team. It’s no surprise, then, that Ford, FCA, and GM are all abandoning key passenger car segments now dominated by import marks. Bigger cars promise fatter margins and safer, bigger customer bull’s-eyes.

Iacocca’s passing closes the books on bold product-oriented statements emanating from the CEO’s office. The closest the automotive industry comes, today, to a CEO-driven approach to the market resides entirely with Tesla Motors CEO Elon Musk – whose company coincidentally defied all skeptics by shipping a record number of Tesla EV’s in its latest quarter reported yesterday.

Still, Musk isn’t making cars for the masses just yet. Iacocca and Chrysler, in his day, were delivering a wide range of cars – including convertibles! – to a very wide audience indeed. At a time when the bean counters increasingly rule the industry it is refreshing to recall the Iacocca of old, circa 1984.

Listening to Iacocca is a nearly incomprehensible blast from the past. Take a listen to his turn as a Chrysler spokesperson in a 1984 television advertisement: https://tinyurl.com/yxaqsssy – Youtube

Here is the transcript – no surprise he was considered a potential presidential candidate at the time.

“A lot of people think America can’t cut the mustard anymore, that quality counts for nothing, and hard work for even less, and commitment, that went out with the hula hoop.

“Well, when you’ve been kicked in the head like we have, you’ll learn pretty quick to put first things first. And in the car business product comes first, and product is what brought us back to prosperity; high mileage, front wheel drive, quality products.

“By the way, with the best safety recall record over the last two full model years of any American cars. Convertibles, they said, nobody wanted, but everybody copied. Sports cars and luxury cars and turbo, so powerful, so efficient, you’ll never go back to V8 again. And a wagon, so versatile, so right for America today, we can’t build enough of them. Not bad for a company that had one foot in the grave.

“Today every man and woman at Chrysler has a commitment, to build cars that will take on the best.

“We will build two sedans this fall, LeBaron GTS and Dodge Lancer that will challenge BMW, Audi, even Mercedes, for thousands less. And next year we will build a small car right here in America with quality that we’re determined will beat the Japanese at their own game and we will build the best backed American cars with five-year or 50,000 mile protection.

“Quality, hard work, commitment, the stuff America was made of. Without them there is no future. I have one and only one ambition for Chrysler, to be the best. What else is there?”

Two car companies do stand out for the innovative products already on the road or in their development pipelines: Volkswagen and Renault. It is notable that Volkswagen is talking of an alliance with Ford Motor Company and FCA has talked of aligning with Renault. Both conversations could open up the North American market to a stream of innovative and unique small cars – including electrified models – that will lead to further erosion of Detroit dominance of the U.S. market.

We miss you, Lee. We miss your vision, your gumption and your tagline: “If you can find a better car, buy it!”

Posted on

Jump-Starting Full-Stack AI

Jump-Starting Full-Stack AI
by Bernard Murphy on 07-03-2019 at 5:00 am
Categories: AI
2 Comments

In the semiconductor world when we hear “full-stack” we think of a chip, chipset or board with a bunch of software, which can be connected to sensors of various types on one end, trained networks in the middle and actuators on the other side. But of course that’s not really a full-stack. The real thing would be deployment of an entire AI system such as an autonomous robot that can pick items from warehouse shelves, or a wearable medical device enabling disease management pathways, or an industry 4.0 process control and monitoring systems. Somebody else builds those, right, but how? This is still a very new domain in which everyone is feeling their way. If you’re not Amazon and you don’t know how to start, or even what expertise you need to spin up in-house to get a prototype working, you’d probably like some help.

The AI Lab Team

That’s where ICURO comes in. They build what they call AI system accelerators, intelligent technology solutions for businesses. I think of it as intelligent system design and prototyping as a service. This is obviously a bit different than regular XaaS services; here you get a full-stack AI system unifying the power of machine learning, machine vision, sensor fusion, embedded processors, robotics, and security to demonstrate immediate value in your business application.

Pulling this off obviously takes more than silicon, software and AI expertise. I talked to Bipin Thomas, President of ICURO at their AI systems lab in Santa Clara. That lab is itself an indicator that this is a different kind of company. While they’re building and prototyping AI products and solutions for their clients, ICURO’s core value is in the range of expertise they have acquired in architecting, developing and integrating those products.

They build on state-of-the-art hardware and software wherever available. So for example they use platforms like NVIDIA Xavier and AMD APU for ML inferencing. They use top of the line 4K cameras, inertial measurement systems, LiDARs, ultrasonic sensors, etc. For ML they connect to standard platforms for neural network definition and training – TensorFlow, Caffe and Darknet. And for navigation they use Visual SLAM and/or LiDAR SLAM together with ORB SLAM for localization. In a different example, a hospital provider used ICURO for pilot studies of health monitoring based on the Apple watch. So you can see that they provide a pretty broad range of AI solutions and services connecting underlying technology capabilities to end-user use-cases.

These are just some examples. As a full-stack AI solution provider, they want to provide help not only to end-users but also to component providers who want to project their value through demonstrator platforms. I know of at least one chip customer who is working with them for exactly this reason. I know of another who is looking for help in building use-case expertise for their general-purpose robot. This domain is so big and complex that very few companies are beyond looking for help; ICURO is already working with several Fortune 500 companies.

To cover all these bases, Bipin has built a team with a wide range of expertise:

  • Machine learning – to define and drive neural network training and optimization for inferencing
  • Sensor fusion – we casually throw this term around but making it work in a real application is still an art
  • Embedded systems – for all aspects of the embedded software stack
  • Edge architectures – for sensing and actuation along with reasonable power, communications and security
  • Mechatronics – for the mechanical aspects of actuation

Bipin is very proud of this full-stack AI systems lab in the heart of Silicon Valley. He has deliberately chosen not to recruit seasoned veterans, even in these domains. Instead he staffs the lab with recent graduates, not locked into fixed ways of solving problems in this still-evolving domain. The lab in his view is his secret sauce, a unique way to architect and build out full-stack AI systems. And he walks this walk. When prospects or partners visit, they don’t get slideware, they get hands-on demos. Which of us wouldn’t take a working demo over death by PowerPoint? You can learn more about ICURO HERE.

Posted on

#56DAC Update – What’s New at Concept Engineering

#56DAC Update – What’s New at Concept Engineering
by Daniel Payne on 07-02-2019 at 10:00 am
Categories: Concept Engineering, EDA

Concept Engineering, DAC56

I first connected with Gerhard Angst of Concept Engineering over 15 years ago, because I was using their SpiceVision PRO tool to visual SPICE netlists received from customer designs to be debugged in a FastSPICE circuit simulator. The ability to visualize a transistor-level netlist was simply essential to quickly understanding what the topology of a totally new netlist was, without having to hand-draw it, which was never a fun or accurate process. At #56DAC I met up with the team to ask them, “What’s New this year?”

NASA-JPL

I love all things space related, so was interested to hear about NASA’s Jet Propulsion Laboratory and how their missions to Mars and Europa, a Jupiter moon are using a couple of tools from Concept Engineering:

  • E-engine (automatic schematic generation engine for aerospace and automotive tools)
  • EEvision (visualization platform for aerospace and automotive)

Engineers at JPL follow a model-based approach that uses requirements to drive all aspects of a new design. Using E-engine and EEvision the development team members will have system and harness visualization abilities, and because the data is in the cloud they can see what they need quickly and it’s always up to date. Engineers won’t have to manually draw schematic diagrams in order to communicate with each other, because the new visualization tools will automatically generate just the portions they need to collaborate with.

The specific JPL projects using these new tools include:

  • Mars Sample Return – robots collect and return samples to Earth
  • Psyche Mission – journey to a metal asteroid between Mars and Jupiter
  • Europa Clipper – does Jupiter’s moon Europa have conditions suited for life

New VISION Features

Customers are constantly asking for new features in order to save time in their engineering tasks, so with version 6.11 of the Vision products they are getting several new abilities.

  • Speed and capacity for the largest SoC designs
  • Split-screen mode for easier debug and cross-probing
  • Selected objects have more extensive reporting
  • Easier visualization of parasitic extracted netlists
  • Better drag-and-drop between apps
  • Improved parsing of Verilog and VHDL designs
  • Parsing of SPICE netlists with macro models
  • Exporting Verilog netlists better supports simulation flows
  • SPICE netlists have automatic logic recognition
StarVision, auto-generated schematic

There are four types of Vision products, it all depends on the level of engineering abstraction that you’re working on:

Summary

The team at Concept Engineering has been busy over the past year and continue to expand the product features of their VISION tools, and the aerospace engineers at NASA-JPL are more effective in their tasks by using more automation instead of manual methods. Visualizing your designs can be quickly done at various levels of abstraction: transistor, gate, RTL. Documentation for service personnel is made easier by always being up to date, instead of behind several versions, because the auto-generated schematics are created directly from the CAD design data.

Schematic created directly from CAD design data

Related Blogs

Posted on

An Important Next Step for Portable Stimulus Adoption

An Important Next Step for Portable Stimulus Adoption
by Daniel Nenni on 07-02-2019 at 5:00 am
Categories: AMIQ EDA, EDA

Portable stimulus has been a hot topic for a couple of years in the EDA and semiconductor industries. Many observers see this approach as the next major advance in verification beyond the Universal Verification Methodology (UVM), and the next step higher in abstraction for specifying verification intent. The basic idea is to create high-level models that can be used by EDA tools to generate test cases automatically. Yes, that sounds rather like the sort of constrained-random simulation tests supported by SystemVerilog, and even longer by the e language, both well-established standards. Let me explain what’s new.

Note first that Portable stimulus is also standardized; Accellera released version 1.0 of the Portable Stimulus Standard (PSS) at the Design Automation Conference (DAC) last year and version 1.0a in February to clean up a few things. But PSS is different from SystemVerilog and e in at least three important ways. I already mentioned the higher level of abstraction, and this enables the portability at the heart of the other two differences. PSS tools can generate test cases that scale from block/IP level through subsystems to complete SoCs/systems, and also from simulation through emulation, prototyping, and actual chips.

A recent post by Jim Hogan provides lots more information on the history and goals of portable stimulus and the standard. It’s easy to see why there’s so much interest in his topic. The idea of writing one abstract, portable model that can generate test cases for every phase of an SoC project is really attractive. I’ve talked with PSS tool vendors Breker, Cadence, and Mentor, and they all assured me that adoption is going well. There’s a fourth vendor in the PSS camp, AMIQ EDA, and my colleague Bernard Murphy discussed their initial support for portable stimulus in a post about six months ago.

Since then, I’ve had several interesting conversations with AMIQ EDA’s CEO, Cristian Amitroaie, about different aspects of their Design and Verification Tools (DVT) Eclipse Integrated Development Environment (IDE) and their Verissimo SystemVerilog Testbench Linter. Cristian mentioned that the initial support they provided for PSS in DVT Eclipse IDE has been expanded, so I talked with him about a key new feature: scenario generation and visualization. Their tool now has the ability to analyze the stimulus being specified in a PSS model and display possible scenarios that satisfy the abstract specification.

Why is this so interesting? For one thing, a large number of valid scenarios can be generated from a single PSS model. It’s not easy for the engineer writing the model to visualize the details of the scenarios that could be generated.  Sometimes there are multiple ways to “solve” a PSS model to generate valid scenarios, and some of them may not be at all obvious (or even intended). The ability to visualize detailed scenarios can be very helpful in terms of determining whether or not the abstract PSS model is correct.

Due to the degree of parallelism available in a modern SoC, there may be dozens of processors and other engines running code, numerous I/O ports sending and receiving data, multiple memories with multiple channels and multiple levels of caches, and a bevy of buses tying all this together. Effective SoC verification requires exercising all this activity simultaneously. PSS models and the testcases based on the generated scenarios have the power to do this, but again it can be hard to picture how this all works without solving for valid scenarios and displaying them. I asked Cristian what happens if their tool cannot generate a valid scenario. He said that DVT Eclipse IDE provides detailed information about the generation process to help users fix the PSS model.

It seems to me that this new solving and visualization feature is a natural extension to the other capabilities that DVT Eclipse IDE offers for PSS code. The tool can parse code and find a wide variety of syntax and semantic errors, including those detectable only when multiple models have been compiled together. It also provides quick-fix proposals, hyperlinks to jump to declarations and usages, context-sensitive auto-completion of PSS constructs, structural views for browsing type and component hierarchies, project database queries, rename refactoring, and source code formatting.

I’ve been convinced for some time that a powerful IDE can make learning a new language much easier and save time in common operations even for the experts. This is certainly true for AMIQ EDA’s PSS support in DVT Eclipse IDE. The language is still novel for many engineers, while features such as scenario generation and visualization benefit both new and advanced users. I’d like to thank Cristian for sharing his thoughts with all of us, and I wish you luck as you adopt PSS.

To learn more, visit https://dvteclipse.com/products/dvt-eclipse-ide

Also Read

With Great Power Comes Great Visuality

Renaming and Refactoring in HDL Code

I Thought that Lint Was a Solved Problem

Posted on

An AI Accelerator Ecosystem For High-Level Synthesis

An AI Accelerator Ecosystem For High-Level Synthesis
by Bernard Murphy on 07-01-2019 at 10:00 am
Categories: AI, EDA, FPGA, Siemens EDA
1 Comment

AI accelerators as engines for object or speech recognition (among many possibilities), are becoming increasingly popular for inference in mobile and power-constrained applications. Today much of this inferencing runs largely in software on CPUs or GPUs thanks to the sheer size of the smartphone market, but that will shift as IoT volumes quickly overtake these familiar devices. IoT applications are generally very cost and power-sensitive, yet also demand higher performance from the inference engine to recognize more objects or phrases in real-time, so that they can deliver a competitive user experience.

Cost, power and performance are generally critical to differentiation for these devices and standard hardware platforms can’t rise to competitive expectations; this is driving the popularity of custom AI accelerators. However there is no standard architecture for these engines. Certainly there’s a general approach – convolutional neural nets (CNNs) or similar networks, but details in implementation can vary widely, in numbers and types of layers, window sizes, word sizes within layers and even in temporal versus spatial architectures.

So how does a system architect go about building differentiation into her CNN engine when she’s not really a hardware expert? One obvious choice is to start the design in an FPGA, at least for prototyping. This defers ASIC complexities to a later stage, but RTL-based design for the FPGA can still be a huge challenge. A much more system-friendly starting point is C++.

Suppose for example you want to build a spatial accelerator – a grid of processing elements (PEs) which can parallel process sliding windows on an image (this approach is getting a lot of press, see for example Wave Computing). You’ll first want to define your base PE design then interconnect these in a grid structure. The PE element needs to read in image data and weights, then compute partial sums. In addition, depending on how you choose to implement communication through the grid, you may forward weight and image data info through the PE or perhaps around the PE. Next you’ll array and interconnect these elements to build up your grid.

All of this can be expressed in a C++ description of the grid, with instances of classes for the various components. There are some limitations in coding to ensure this can be mapped to hardware, for example word widths are going to have to map to real hardware, and you’ll want to experiment with these widths to optimize your design. This is where the Catapult ecosystem helps out.

You don’t want to start with basic C++ datatypes and functions because these can’t always be optimally mapped; for example, basic C++ doesn’t offer word support with arbitrary widths and general-purpose packages that do won’t natively connect to hardware. The AI ecosystem instead provides predefined HLS (high-level synthesis) datatypes as C++ classes with overloaded operator functions to map your C++ description to a hardware equivalent, while also allowing you to tune in parameterizations consistent with that mapping.

It also provides a math library, including not only the usual math functions for those datatypes but also matrix and linear algebra functions common in neural net computation. Such functions can come in different implementation options:, such as fast with some small error or a little slower with higher accuracy. As you’re running your C++ trials you can easily experiment with tradeoffs like this. Functions provided cover all the usual list for neural nets, including PWL functions for absolute value, log, square root, trig, activation functions for tanh, sigmoid and leaky ReLU, and linear algebra functions like matrix multiply and Cholesky decomposition A lot of these functions also have MatLab reference models which you will probably find useful during your architectural analysis.

You also get a parameterized DSP library for functions like filters and Fourier transforms and an image processing library, configurable for common pixel formats and providing functions you are likely to need, like color conversion, image scaling and windowing classes for 2D convolution.

So pretty much you’ve got everything you need to take you from an input image (or speech segment) through widowing, to all the CNN functions you’re going to need to complete your implementation through to identification. All in C++, using which you can do initial tuning in MatLab. You can experiment with and verify functionality and performance at this level (waaaay faster than simulation at RTL) and, when you’re happy, you can synthesize directly into an RTL implementation where you can characterize power and area.

Since your accelerator will sit in a larger system (an FPGA or an SoC), you need to connect with that system through standard interfaces like AXI. Catapult HLS takes care of you here through interface synthesis. Ultimately, at least for your prototype, you can then map your design to that FPGA implementation so you can check performance and accuracy at real-time speeds.

To round this out, the ecosystem provides a number of predefined toolkits/reference designs: for pixel-pipe video processing, for 2D convolution based on the spatial accelerator grid structure I mentioned earlier, and for tinyYOLO object classification. No need to build these from scratch; you can start with the toolkits and tweak to get to the architecture you want.

This is a pretty complete design solution to help bridge the gap between AI system design expert needs and the hardware implementation team. You should check it out HERE.

Posted on

Two Fun Things To Do at SEMICON West on July 9, 2019

Two Fun Things To Do at SEMICON West on July 9, 2019
by Randy Smith on 07-01-2019 at 10:00 am
Categories: EDA, ESD Alliance, Events, IP

 

I will be at SEMICON / EE Design West on Tuesday, July 9, 2019, and so should you!

Quantum computing will be a hot topic at SEMICON West and on Tuesday, July 9, the IBM Quantum Computer will be on display at the Smart Design Pavilion in the South Hall (Moscone Center) from 10:00am to 5:00pm. It looks like no other computer I have ever seen and should make for a fun diversion at SEMICON West.

What is quantum computing? It is a new approach to logic, or a new approach to computing, depending on how you look at it. Many of the tougher problems we would like to solve today just cannot be run on even the biggest classical computers. The world needs a new kind of computer. Quantum computers utilize the quantum mechanical phenomena of superposition and entanglement to create states that scale exponentially with number of qubits, or quantum bits. That is more than a bit to wrap your mind around. But we all should starting learning about it now.

Of course, IBM has been developing a Full Stack Quantum Software package since a computer isn’t not useful if you cannot program it. You can even try it out now. There’s a lot to see and hear about quantum computing at SEMICON WEST, including a TechTALK and a keynote. You can get more info on the IBM Q computer activities at SEMICON WEST here, and more details on IBM’s quantum computing efforts here.

Every summer for more than a dozen years, the Heart of Technology (HOT) has thrown a party to raise money for a worthy charity, typically one aiding children or young adults. This year will be no different as the HOT event of the summer will take place on Tuesday, July 9 at the John Colins Lounge located at 138 Minna Street in San Francisco, coinciding with SEMICON West / ES Design West being held at nearby Moscone Center. The event will run from 5:30pm to 10:00pm. Click the link above to register in advance.

Heart of Technology is a charity accelerator helping local charities hold special events, sometimes far larger than any events they would typically undertake. Jim Hogan is the leader and founder of HOT. I have helped Jim with these events for a long time. We now have a large number of volunteers to help us put on these events, and of course, we are very grateful to the companies that sponsor these events.

We seek donations from many local companies in the electronics industry, including EDA and semiconductor IP. The official tally is over $180k since 2012, but I am sure it is much more, we just never really kept track as the funds went straight to the charities. I remember we raised over $30k (from an auction and gate receipts), plus donated food, at an event supporting Second Harvest in San Jose around 2004. Some recent events have given more than $50k to local charities and scholarship funds. I imagine the correct number is likely close to half a million dollars by now.

This year’s event will have a slightly different focus. “We are always running into inequality with gender in sciences and engineering. The aim is to get more girls and women interested in the sciences. The SEMI organization has a foundation that has such a program, so that’s what we’re raising money for this year.” Several corporate donations have already come in, but we can use everyone’s help. We are expecting a strong turnout this year as the event becomes accessible to an audience far larger than DAC.

This year’s venue is also a bit smaller than usual as we deal with the transition year in EDA trade shows. If you are planning to go, badge holders at ES Design West and SEMICON West will be admitted with a suggested minimum $20 donation. Other guests can attend for a donation of $50. The venue is small, so please arrive as early as you can. The Methodics Ensemble, as well as the Dead Sea Fish, will be playing. Members of Jim Hogan’s band, Vista Roads, will be in attendance and may sit in with the bands that are playing. And I know from our past events, a good time will be had by all.

Now, go register for SEMICON West.