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The Wilf Corrigan Fairchild P&L Review

The Wilf Corrigan Fairchild P&L Review
by John East on 07-15-2019 at 6:00 am
Categories: John East
7 Comments

The “20 Questions with John East” series continues

In 1973 plus or minus a year or so I was working as a supervising engineer in one of the bipolar digital product groups.  My boss was a man named Jerry Secrest.  He was a great boss – he taught me most of what I knew about ICs in my youth. Jerry had responsibility for a product line.  That meant that the Fab, the product and process engineers, and the test area all were under him.  It also meant that he had P&L responsibility.  That sounds like a good thing, doesn’t it?  It wasn’t!!!

P&L responsibility forces you to open your eyes to how life really is.  Sometimes reality isn’t fun.  It’s not hard to find someone today writing that profits are evil and the people who try to make them are even more evil.  But reality tells a different story.  If you’re a private company,  to get the company going and keep it going you have to raise money.  To do that, you have to tell the potential investors that once you’re up and running, you’re going to be making nice profits and that the profits will grow over time.  If you don’t,  they won’t invest.  Going back later and telling them, “I was only kidding” is ill-advised!!

If you’re a public company,   the same argument holds true, but on steroids!  People buy your stock because they think it’s going to go up.  Why do they think that?  Because you led them to believe it.  In the long run, stocks go up because earnings go up, so it’s your job to make earnings go up.  There’s no way you could go back to the shareholders and say,  “Gee.  I changed my mind.  Profits are evil.  I’m not going to try to make any.  My plan is to make the stock go down.”  What, if instead of being the CEO,  you owned some of that stock? You’d kick the CEO out in a nanosecond.  Then you’d sue him    — and you’d win the suit!

Oh.  One other thing.  In both cases,  if you lose money long enough,  you eventually run out and go broke.  So   — it’s important to be profitable!!!  Yes.  You also have a responsibility to the people who work there and another to the extended community.  Trying to take care of all three simultaneously was the hardest thing I ever did!!!!  But  — when the dust settles  — — it’s important to be profitable!!!

Sometimes capitalism sucks  —  but  I’ve been in most of the formerly communist countries back when they were just coming out of communism.  They were absolute economic disasters.  So, capitalism may well suck,  but all the other systems that I’m aware of suck more.  Far more!!  By the way.  I am not affiliated with either political party.  They both aggravate me!

Back to the story:  Each operation at Fairchild had a regular P&L review with Wilf Corrigan, then a Vice President and later to be Fairchild’s CEO. Besides Wilf, his top financial guy and several people from the operation being reviewed attended. I worked in the Digital Integrated Circuits group (DIC) which was run by a guy named John Sussenburger (We called him Suss).  Jerry worked under Suss.  Suss worked under Wilf.  The financial reviews looked at Sussenberger’s P&L and its component P&Ls.  (Tom Longo,  Paul Reagan, and Dave Deardorf were also involved in the organization at various times in those days,  but I don’t recall any of them being in the meeting)

Fairchild had a thing they called their HiPot List. (High Potential List) You were put on the HiPot list if you were a high potential employee who seemed to have the ability to work your way into upper management.  To my great delight, in 1971 or 1972 they added me to that list. Wilf had put in a rule that at each review a different person from the HiPot list should come to get some seasoning.  One day Jerry told me that my turn in the barrel had come. It was my chance to go to the review.

I went to the conference room at least 20 minutes before the start time. There was a large potted plant at the back of the conference room. I figured out that one of the chairs in the back was partially hidden from view by that potted plant. Naturally I took that chair.  (I was scared to death of all the Fairchild high-level managers) Then I waited. After a while the real attendees came filing in and the meeting began. Wilf Corrigan is astute! There is no tricking Wilf with the numbers. They would put up very complex foils absolutely full of numbers and Wilf would immediately zero in on the number that made a difference

He was very direct, but very polite. No screaming, shouting or table pounding even though DIC was losing money. We all understood that Wilf Corrigan didn’t like losing money, so the review didn’t have a good feel to it  –  all the attendees were on pins and needles.  But – it didn’t seem to be a problem. Wilf was calm and cordial.  He very calmly went about getting an understanding of what was going on.   When all the data had been presented, Sussenberger asked Wilf if he had any questions.  I thought, “Wow. This isn’t so bad. We’re losing money, but Wilf understands. Nobody got beaten up or fired. What was I worried about?”

Wilf said, “Yes. A couple of questions:  How much money did you say you were losing?”

(I don’t remember the actual numbers so I’ll make some up.)

John: “Oh. We’re losing about a million dollars, Wilf.”

Wilf: “What does your average employee make, John?”

John: “Gee I don’t know exactly, but I’ll guess about $20,000.”

Wilf:  –“Hmmm. That comes to 50 people, doesn’t it?”

John: “Well, you could look at it that way, Wilf.”

Wilf: ‘‘I do look at it that way, John.”

Wilf  “OK. I don’t have any more questions, but John, I’m planning to do you a favor.”

John: “What’s that, Wilf?”

Wilf: “Tonight I’m going by the hardware store on my way home. I’m going to buy one of those clicker/counters….. you know the little mechanical things with a button. Each time you hit the button with your thumb it ups the count by one.”

John: “Great Wilf!  That’s great!!!  Sounds really good!!! …  I like that!!!       …………..  ……………………..   but … what are you going to do with that?”

Wilf: “I’m going to go into your building Monday morning. I’m going to stand in the main hall. Each time someone walks by me I’m going to ask him if he works for John Sussenburger.  If he says ‘Yes’, I’m going to say, ‘You’re fired’ and click the button. When the count gets to 50, you’ll be profitable!   —– John, you’re really going to enjoy running a profitable business!”

I stayed out of the hall that Monday morning!

Wilf Corrigan went on to become the founder / CEO of LSI Logic

Next week:  The demise of Fairchild.

See the entire John East series HERE.

Pictured:  Wilf Corrigan.

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AI Chip Landscape and Observations

AI Chip Landscape and Observations
by Shan Tang on 07-14-2019 at 8:00 am
Categories: AI

It’s been more than two years since I started the AI chip list. We saw a lot of news about AI chips from tech giants, IC/IP vendors and a huge number of startups. Now I have a new “AI Chip Landscape” infographic and dozens of AI chip related articles (in Chinses, sorry about that :p).

At this moment, I’d like to share some of my observations.

First and foremost, there is no need to argue about the necessity of dedicate AI hardware acceleration anymore. I believe, in the future, basically, all chips will have AI acceleration design inside. The only difference is how much area you will put there for AI. That is why we can find almost all of the traditional IC/IP vendors in the list.

Non-traditional chip makers designing their own AI chip has become a common practice and showing their special power in more and more cases. Tesla’s FSP chip could be highly customized to their own algorithms, which is evolving constantly by the “experience” of millions of cars on the road, and enforced with the help of Tesla’s strong HW/SW system teams. How do others compete with them? Google, Amazon, Facebook, Apple, Microsoft are working similarly, with the real world requirements, the best understanding of the application scenarios, strong system engineering capabilities, and deep pocket. Their chips are of course easier to succeed. How do traditional chip makers and chip start-ups compete with them? I think these will be the key questions that will shape the future of the industry.

A huge number of AI chip startups emerge, which outnumbered any other segments or any other time in the IC industry. Although it is slow down a bit now, we still hear money-raising news from time to time. The first wave of startups is now moving from showing architecture innovations to fighting in the real world to win customers with first generation chip and toolchain. For latecomers, “to be different” is getting harder and harder. Companies who use emerging technologies, such as in-memory computing/processing, analog computing, optical computing, neuromorphic, etc., are easier getting attention, but they have a long way to go before productizing their concept. In the list, you can see that, even in these new areas, there already are multiple players. Another type of differentiation is to provide vertical solutions instead of just the chip. But, if the technical challenge of such vertical applications is small, then the differentiation advantage is also small; for some more difficult applications, such as automatic driving, the challenge they face is the need to mobilize a large number of resources to do the development. Whatever, the startups have to fight for their futures. But, if we look at the potential usage of AI in almost everywhere, it is worth betting.

“Hardware is easy, software is much more difficult” is something we all agree on now. The toolchain that comes with the chip is the biggest headache and is with big value as well. In many speeches from AI chip vendors, they spend more and more time introducing their software solutions. Moreover, the optimization of software tools is basically endless. After you have single-core toolchain, you need to start thinking about multi-core, multi-chip, multi-board solutions; after you have compiler or library for neural network, then you have to think about how to optimize non-NN algorithm in the heterogeneous system for more complex applications. On the other hand, it is not just a software problem at all. You need to figure out the best tradeoff of software and hardware to get optimized results. From last year, we see that more and more people working on the Framework and Compiler for optimization, especially the compiler part. My optimistic estimate is that the compiler for just NN part will be mature and stable within a year. But other issues I mention above require continuous efforts and much longer time.

Among benchmarks of AI hardware, the most solid work we saw is MLPerf (just released the Inference recently) with most of the important players joining. The problem of MLPerf is that the efforts of the deployment are not trivia. Only a few large companies have submitted the training results. I am looking forward to more results in the coming months. At the same time, AI-Benchmark from ETH Zurich got attention, which is similar to the traditional mobile phone benchmark, using the results of running application to score the chip’s AI ability. Although it is not fully fair and accurate, the deployment is simple and it already covered most of the Android phone chips.

The AI chip race is a major force to drive the “the Golden age of architecture”. Many failed attempts 20 or 30 years ago seem to be worthy to revisit now. The most successful story is the systolic array, which is used in Google’s TPU. However, for many of them, we have to be cautious to ask: “Is the problem cause its failure in the past is gone today?”

Similar to other segments of AI industry, the speed of adopting academic works into the business world is unprecedented. The good news is that new technologies can get into products faster, and researchers can get rewards quicker, which could be a great boost to the innovations. In most cases, academic research focuses on a breakthrough at one point. However, implementing a chip and its solutions requires a huge amount of engineering works. So, the distance in between is actually very large. Nowadays, people more like talking about innovation at one point, but neglect (maybe intentionally ) the “dirty work” required to implement the product. This could be dangerous to the investors and the innovators.

Last but not least, one interesting observation is that the AI chip boom is significantly driving the development of the related areas, such as EDA/IP, design service, foundry, and many others. We see the progress in the areas, like new types of memory, packaging (chiplet), on-chip/off-chip networks, are all speeding up, which may eventually lead to the next round of exciting AI chip innovations.

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Are the 100 Most Promising AI Start-ups Prototyping?

Are the 100 Most Promising AI Start-ups Prototyping?
by Daniel Nenni on 07-12-2019 at 10:00 am
Categories: AI, Prototyping, S2C EDA

I came across a report on the 100 most promising AI start-ups. The report claimed that CBInsights had “selected the 100 most promising AI start-ups from a pool of 3K+ companies based on several factors …”  Wait, what … 3K+ companies!?!?  This was a stunning reminder of the sheer magnitude of what is shaping up to be a veritable tsunami of AI start-ups.  Combine this tsunami with a large number of inquiries from early stage AI start-ups asking S2C for help with FPGA prototyping, and it’s becoming abundantly clear that the demand curve for modestly priced FPGA prototyping products and services will be shaped like a hockey stick, absolutely.

Many of these start-ups are at a complete loss as to what’s required to plan for, implement, and execute an FPGA prototype.  So, for what it’s worth, here are a few hindsight considerations from one experience I had with FPGA prototyping at a start-up developing a small but very complex SoC;

  1. Start FPGA prototype planning early and involve all SoC stakeholders … chip design verification, silicon bring-up, firmware development, etc…
  2. Write an SoC Product Requirements Document (PRD) that all stakeholders clearly understand, and agree to … and establish a revision control process that keeps it current as the requirements evolve through the project.
  3. Remember that the SoC, not the FPGA prototype, is the mission … so, set reasonable expectations for FPGA prototype project scope and facilitate the FPGA prototype project with sufficient resources, deep FPGA prototyping expertise, and aggressive but achievable milestones.

Of course, the project I reference did none of the above, that’s why I referred to them as “hindsight considerations”.  The FPGA prototype “vision” for pre-tapeout verification was to use the FPGA prototype in parallel with simulation-based verification for higher verification coverage, and then make the prototype available to firmware developers for early firmware bring-up and get it all done before tapeout.

This particular design verification project was challenged from the beginning.  As it turned out, not all simulation jockeys believed in FPGA prototypes, and there was some passive aggressive behavior that impacted the success of the overall SoC verification effort.  The “golden netlist” (the one used for tapeout) for SoC simulation always needs to be modified for the FPGA implementation to accommodate the intrinsic FPGA clocking, embedded memory, embedded IP, and DFT physical constructs.  The burden of understanding the netlist differences, what impact they will have on the test results when the FPGA prototype is subjected to the same testing as the golden netlist, and which netlist differences to ignore and which need special attention, should be a team responsibility.

This project came to appreciate the need for a robust netlist versioning process for modifying the netlist throughout the verification project to assure that the two verification platforms stay aligned when design bugs are fixed and PRD changes are introduced into the design during the development process.  The importance of a robust SoC bug reporting platform (Bugzilla, Jira, etc.) was also really appreciated late in the project when the bug discovery rate slowed to a trickle to minimize one of the two verification teams spending a lot of time isolating, fixing, and verifying an SoC bug that the other team had already fixed weeks ago.

Then, there was the point at which the FPGA prototype platform was handed over to the firmware team … this was a rude awakening.  Unlike the use of the FPGA platform for design verification, the firmware team expects the FPGA platform to actually work according to the PRD!  The firmware team has no patience for a software validation platform that doesn’t work, and they don’t have the skill set nor the inclination to try to understand why their software is not working on the hardware.  They simple “kick” the FPGA prototype back to the hardware guys and tell them to “fix it”.

The first attempts to run firmware on the FPGA prototype can be plagued by elusive problems that are as simple as how the hardware comes out of “reset”.  The FPGA prototyping team must plan to support the firmware team during the inevitable ramp-up of firmware validation on the FPGA prototype platform.  If firmware validation is on the critical path to tapeout, as it was for this project, days and weeks matter.

As a strong foundation to any FPGA prototyping project, high quality, reliable FPGA hardware is an absolute must.  The SoC verification project is challenging enough without having to worry about the underlying FPGA hardware.  S2C has been building and delivering FPGA prototyping hardware and software since 2005, and each generation has been an improvement on the previous generation.  S2C supports Intel and Xilinx FPGAs, and offers Single, Dual and Quad FPGA versions of its Prodigy Logic Systems.

To get a quick S2C quote click here.

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The Coming Tsunami in Multi-chip Packaging

The Coming Tsunami in Multi-chip Packaging
by Tom Dillinger on 07-12-2019 at 6:00 am
Categories: Foundries, Intel Foundry
6 Comments

The pace of Moore’s Law scaling for monolithic integrated circuit density has abated, due to a combination of fundamental technical challenges and financial considerations.  Yet, from an architectural perspective, the diversity in end product requirements continues to grow.  New heterogeneous processing units are being employed to optimize data-centric applications.  The traditional processor-memory interface latencies are an impediment to the performance throughput needed for these application markets.  Regular Semiwiki readers are aware of the recent advances in advanced multi-chip package (MCP) offerings, with 2.5D interposer-based and 3D through-silicon via based topologies.

Yet, it wasn’t clear – to me, at least – how quickly these offerings would be embraced and how aggressively customers would push the scope of multi-die integration for their design architectures.  I recently had the opportunity to attend an Advanced Packaging Workshop conducted by Intel.  After the workshop, I concluded that the rate at which advanced MCP designs are pursued will accelerate dramatically.

At the workshop, the most compelling indication of this technology growth was provided by Ram Viswanath, Vice President, Intel Assembly/Test Technology Development (ATTD).  Ram indicated, “We have developed unique 3D and 2.5D packaging technologies that we are eager to share with customers.  Product architects now have the ability to pursue MCP’s that will offer unprecedented scale and functional diversity.”   The comment caught the audience by surprise – several members asked Ram to confirm.  Yes, the world’s largest semiconductor IDM is enthusiastically pursuing collaborative MCP designs with customers.

For example, the conceptual figure below depicts a CPU, GPU, VR accelerator, and memory architecture integrated into a package that is one-sixth the dimension associated with a discrete implementation.  The size of this organic package is potentially very large – say, up to 100mm x 100mm.  (Intel’s Cascade Lake server module from the Xeon family is a 76mm x 72.5mm MCP containing two “full reticle-size” processor die.)

For the cynical reader, this was not the same atmosphere as the previous announcement of the fledgling Intel Custom Foundry fab services.  There was a clear, concise message that emerging data-driven applications will want to leverage multi-chip package integration (around an Intel CPU or FPGA).  The Intel ATTD business unit is committed to support these unique customer designs.

The rest of this article will go into a bit of the MCP history at Intel, with details on the 2.5D and 3D package technologies, as well as some future packaging research underway.

MCP History

After the workshop, I followed up with Ram V., who provided a wealth of insights into the R&D activity that has been invested in MCP technology development at Intel.  He indicated, “There is extensive experience with multi-chip packaging at Intel.  For example, we are shipping a unique embedded silicon bridge technology for inter-die package connectivity, which has been in development for over a decade.  This capability to provide wide interface connectivity between die offers low pJ/bit power dissipation, low signal integrity loss between die, and at low cost.”  The figure below depicts the interconnect traces between the microbumps of adjacent die edges – a key metric is the (product of the) areal bump density and routable embedded traces per mm of die perimeter. 

“The technology development focused on embedding a silicon bridge into the panel-based organic package assembly flow.  The x, y, z, and theta registration requirements for the bridge are extremely demanding.”, Ram continued.

Ram showed examples of Stratix FPGA modules with HBM memory utilizing the embedded bridge.  “This product roadmap began with just a few SKU’s when Intel was fabricating Altera FPGA’s, prior to the acquisition.   FPGA applications have grown significantly since then – there are now MCP offerings throughout the Stratix product line.”  He also showed (unencapsulated) examples of the recently-announced Kaby Lake CPU modules with external GPU, leveraging embedded bridges between die.

“Any significant assembly or reliability issues with the die from various fabs?”, I asked.

“This technology is the result of a collaborative development with suppliers.”, he replied.  Pointing to different die in the various MCP modules, he continued, “This one is from TSMC.  This one is from GF.  Here are HBM memory stacks from SK Hynix.  We have worked closely with all the suppliers on the specifications for the micro-bump metallurgy, the volume of bump material, the BEOL dielectric material properties, die thickness and warpage.  All these sources have been qualified.”

EMIB

The embedded multi-die interconnect bridge (EMIB) is a small piece of silicon developed to provide wide interconnectivity between adjacent edges of two die in the MCP.  The EMIB currently integrates four metallization planes – 2 signal and 2 power/ground (primarily for shielding, but could also be used for P/G distribution between die).

Additionally, the SI team at Intel has analyzed the signal losses for different interconnect topologies of signal and ground traces of various lengths – see the figure below.

Ravi Mahajan, Intel Fellow, provided additional technical information on EMIB.  He indicated the metal thickness of the EMIB planes is between that of silicon die RDL layers and package traces, achieving a balance between interconnect pitch and loss characteristics.  “We’re at 2um/2um L/S, working toward 1um/1um.  Our SI analysis for the EMIB suggests up to an 8mm length will provide sufficient eye diagram margin.  Conceptually, an EMIB could up to ~200mm**2.”  (e.g., 25mm between adjacent die edges X 8 mm wide)

Currently, the design and fabrication of the bridge is done by Intel ATTD – there is no external design kit, per se.  “The development of the I/O pad floorplans for the adjacent die with the embedded bridge at ATTD is a collaborative effort.”, Ram indicated.  “There is also significant cooperation on the design of the VDDIO and GNDIO power delivery through the package and around the EMIB to the perimeter bump arrays on the die.  Intel ATTD also does the thermal and mechanical integrity analysis of the composite package design.  As the thermal dissipation levels of the emerging markets for MPC’s can be high, and due to the different thermal coefficient of expansion between the die and EMIB silicon and the organic substrate, thermal and mechanical analysis of the microbump attach interface is critical.”

It is probably evident, but worth mentioning that the presence of the EMIB silicon in the package does not interfere with the traditional process for adding surface-mount passives to the overall assembly (e.g., decoupling caps).  At the workshop, the support for backside package metal loop inductors and SMT caps was highlighted – “Intel CPU packages have integrated voltage regulation and voltage domain control since the 22nm process node.  The inductor and capacitor elements on the package are part of the buck converter used in the regulator design.”, Ram indicated.  Customers for Intel MCP designs would have this capability, as well.

Note the characteristics of the EMIB-based design differ considerably from the 2.5D package offerings utilizing a silicon interposer.  On the one hand, the Si interposer allows greater flexibility in inter-die connectivity, as the interposer spans the extent of the entire assembly.  (Newer 2.5D offerings are ‘stitching’ the connection traces between reticle exposures to provide an interposer design greater than the 1X maximum reticle field dimensions.)  Conversely, the EMIB approach is focused on adjacent die edge (wide, parallel) connectivity.  The integration of multiple bridges into the conventional package assembly and final encapsulation flow enables a large area field – e.g., a 100mm X 100mm dimension on a 500mm X 500mm organic substrate panel that was mentioned during the workshop.  The EMIB with organic substrate provides a definite cost optimization.

3D “Foveros”

With the Lakefield CPU product family, Intel introduced 3D die-stacked package offerings, utilizing through silicon vias.  The figure below illustrates the 3D die stacks.

Advanced packaging R&D investment is focused on reducing both the TSV and microbump pitch dimensions – currently at a 50um pitch, heading to ~30-35um pitch.  This will necessitate a transition from thermo compression bonding to a unique “hybrid bonding” process – see the figure below.

Whereas thermo compression bonding utilizes pressure and temperature to meld exposed pad metallurgies on the two die faces, hybrid bonding starts with a (somewhat esoteric) polishing process to provide pad metals with precisely controlled “dishing” of a few nanometers at the die surface.  The bonding step utilizes van der Waals forces between the (hydrophilic, extremely planar) die surfaces, then expands the metals during annealing to result in the pad connection.

Another key 3D packaging R&D concern centers around scaling the (base) die thickness – the goal for advanced 3D packages is to aggressively scale the Z-height of the final assembly.  “Thinning of the stacked die exacerbates assembly and reliability issues.”, Ravi M. highlighted.  As an interesting visual example, he said, “Consider the handling and warpage requirements for die no thicker than a sheet of A4 paper.”  (Starting 300mm wafer thickness:  ~775um;  A4 paper sheet thickness:  ~50um)

In the near future, the ability to combine multiple 3D die stacks as part of a large 2.5D topology will be available, a configuration Intel ATTD denoted as “co-EMIB”.  The figure below illustrates the concept of a combination of 3D stacked die with the embedded bridge between stacks.

Chiplets, KGD’s, and AIB

The accelerated adoption of MCP technology will rely upon the availability of a broad offering of chiplets, in a manner similar to the hard IP functionality in an SoC.  As mentioned above, the Intel ATTD team has already addressed the physical materials issues with the major silicon sources, to ensure high assembly/test yields and reliability.  Yet, the electrical and functional interface definition between chiplet I/O needs an industry-wide focused effort on standardization, to ensure chiplet interoperability.

Intel has released the AIB specification into the public domain, and is an active participant in the DARPA “CHIPS” program to promote chiplet standards.  (DARPA link, AIB link — registration required)  Somewhat surprisingly, the IEEE does not appear to be as actively engaged in this standard activity – soon, no doubt.

At the workshop, the Intel ATTD team indicated that internal activities are well underway on the next gen chiplet interface spec (MDIO), targeting an increase in data rate from 2Gbps to 5.4Gbps (at a lower voltage swing to optimize power).

MCP product designs will continue, but the growth in adoption necessitates a definitive standard – an “Ethernet for chiplet interconnectivity”, as described by Andreas Olofsson from DARPA.

There is another facet to chiplet-based designs that was discussed briefly at the workshop.  The final, post burn-in test yield of the MCP will depend upon the test and reliability characteristics of the known good die (KGD) chiplets.  The ATTD team indicated that Intel has made a long-standing (internal) investment in production ATE equipment development.  One of the specific features highlighted was the capability to perform accelerated temperature cycling testing at wafer level, to quickly identify/sort infant fails – this the resulting KGD forwarded to package assembly will not present a major yield loss after final burn-in.  The suppliers of chiplet “IP” will also certainly need to address how to provide high reliability die, at low test cost.

Futures

The final workshop presentation was from Johanna Swan, Intel Fellow, who described some of the advanced packaging R&D activities underway.  The most compelling opportunity would be to alter the trace-to-via connectivity process.  Rather than the large via pad-to-trace size disparity depicted in the figure above, a “zero misaligned via” would enable significant improvement in interconnect density.  The figure below illustrates the current package trace-via topology, and the new ZMV trace-via connection at 2-4um trace widths.

The current epoxy-based package panel utilizes laser-drilled vias – to realize a ZMV, a new technology is under research.  (Johanna indicated that photoimagable materials of the polyimide family would provide the via density, but that materials, process, and cost constraints require staying with epoxy-based panels – a unique via-in-epoxy process is needed.)  If the ZMV technology transitions to production, the MCP interconnect (line + space) trace density would be substantially increased – when combined with improvements in microbump pitch, the system-level functionality realizable in a large MCP would be extremely impressive.

Summary

There were three key takeaways from the workshop.

  • Heterogeneous multi-chip (die and/or chiplet) packaging will introduce tremendous opportunities for system architects to pursue power/perf/area + volume/cost optimizations.
  • The Intel EMIB interconnect bridge at die interfaces offers a unique set of cost/size/complexity tradeoffs compared to a 2.5D package incorporating a silicon interposer.
  • The Intel ATTD team is committed to supporting their advanced 2.5D, 3D, and merged (co-EMIB) technologies for customers seeking unique product solutions to data-driven markets.

Frankly, in the recent history of microelectronics, I cannot think of a more interesting time to be a product architect.

-chipguy

 

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HBM or CDM ESD Verification – You Need Both

HBM or CDM ESD Verification – You Need Both
by Tom Simon on 07-11-2019 at 11:00 am
Categories: EDA, Magwel

In the realm of ESD protection, Charged Device Model (CDM) is becoming the biggest challenge. Of course, Human Body Model (HBM) is still essential, and needs to be used when verifying chips. However, a number of factors are raising the potential losses that CDM events can cause relative to HBM. These factors fall into two categories: ESD event causes and effects, and difficulty predicting in advance if ESD protections are sufficient and effective. Let’s address each of these in turn.

HBM contemplates an individual pin coming in contact with a charged object, such as a person’s hands. The other requisite condition is that there is a path to ground on another pin. Of course, there might be multiple pins affected in a single real-world event, but testing can be compartmentalized down to two pins at a time. With automated handling, individual ICs are rarely handled by human hands, reducing the likelihood that a pin will be exposed to electrostatic charge.

Even so, protections against HBM type events are very important for chip yield and reliability. There are many other scenarios, during handling and in the field where a device might face a high current ESD discharge. HBM testing can also serve as a proxy for other types of ESD related events. So, we see there is a continued need for adding and verifying protections for HBM.

On the other hand, automated chip handling can subject IC packages to tribo-electric charging as they move through the manufacturing and board assembly processes. This charge build-up can cause big problems once a ground path becomes available. Most often this occurs when one or more pins come in contact with grounded metal. Unlike HBM, the discharge can occur nearly anywhere in the IC. When the package is charged, it induces a capacitive charge build up on large nets on the IC itself. Stored charge is distributed along these nets and any capacitive devices connected to them. Once a conduction path is created large amounts of stored charge begin to flow along these wires. Voltage gradients created during discharge events can subject ESD and core devices to large voltage differentials. Also, even though CDM current pulses are very short their amplitudes can be large leading to thermal failures in thin wires and in triggered devices.

Leading edge designs have several traits that increase the severity of CDM issues. Large IC’s create the need for bigger packages, which can accumulate more charge. The same can be said for the larger nets found in these designs. Additionally, supply nets in FinFET designs are longer and narrower than in earlier nodes. During discharge events, large voltage gradients can occur across these nets, which can damage the smaller and more sensitive advanced node devices.

Both HBM and CDM create challenges for verification teams prior to tape out. Some issues are common to both types of events, others arise or are exacerbated by the nature of CDM events. ESD discharge events are dynamic by their very nature. One or more devices may trigger. It is important to make a full accounting of which devices are actually triggered. Current flows and voltages will be highly dependent on which devices trigger and where charge is stored. Some ESD devices may exhibit snap-back behavior, which rules out the use of ordinary circuit simulators. Instead, a specialized dynamic simulator is necessary to capture device triggering and the resulting voltage build-up afterwards.

The Fieldview from Magwel’s CDMi shows a violation with high voltage built up across the terminals
of a device during a CDM discharge event

The metal structures of the involved nets do not look or act like simple lumped loads. Supply nets are often made up of wide metal and have complex current flow. This makes the methods used for extraction and simulation critical for obtaining accurate results.

Magwel has added a CDM simulation and verification tool to its ESD suite, which previously addressed HBM. Their successful HBM tool, called ESDi, has given them years of experience dealing with the fundamental issues of usability, performance and quality of results. Magwel is known for its highly accurate solver based extraction engine. Their special purpose simulation engines are also a key technology that enabled the development of their CDM offering, CDMi.

CDM protection is often used on large designs, to accommodate this Magwel R&D has rolled out a number of performance enhancements that offer much higher throughput. CDMi also takes advantage of parallel processing to ensure better runtimes. Error reporting that avoids an overload of false errors and debugging play a vital role in overall productivity, so Magwel has used its experience in this area to provide easy to use reporting and a cross-linked layout and field view capability that helps users identify the source of design issues.

Because of its unique solver based technology and their extensive experience in the ESD field, Magwel is well positioned to provide an effective solution for CDM protection network simulation and verification. With the rollout of the CDMi product and the level of interest it has garnered, it seems that Magwel is on the right track. The Magwel website has more information on CDMi and is well worth looking over.

About Us
Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com

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Konica Minolta Talks About High-Level Synthesis using C++

Konica Minolta Talks About High-Level Synthesis using C++
by Daniel Payne on 07-11-2019 at 8:00 am
Categories: EDA, Siemens EDA

Konica Minolta printer

In the early days of chip design circa 1970’s the engineers would write logic equations, then manually reduce that logic using Karnaugh Maps. Next, we had the first generation of logic synthesis in the early 1980’s, which read in a gate-level netlist, performed logic reduction, then output a smaller gate-level netlist. Logic synthesis then added the capability to move a gate-level netlist from one foundry to another. In the late 1980’s logic synthesis allowed RTL designers to write Verilog code and then produce a gate-level netlist. Ever since that time our industry has been searching for a design methodology even more productive than RTL coding, because a higher-level design entry above RTL entry could simulate quicker, have a higher capacity and even reach a larger audience of system-level users that don’t want to be encumbered with the low-level semantics of RTL coding.

High-Level Synthesis (HLS) is an accepted design paradigm now, and the engineers at Konica Minolta have been using C++ as their design entry language for several years while designing multi-functional peripherals, professional digital printers, ultra-sound equipment for healthcare and other products.

The original C++ design flow used is shown below using the Catapult tool from Mentor – a Siemens business, with benefits like 100X faster simulation times than RTL:

Even with this kind of C++ flow, there are some extra steps and issues, like:

  • Manually inspecting algorithm code takes too much time.
  • Code coverage with GCOV produced no insight for synthesizable C++ code, plus no expression, toggle and functional coverage analysis.
  • Manual waivers were required to close coverage.

The Catapult family of tools extends beyond just C++ synthesis, so more of these tools were added, as shown below highlighted in green:

Let me explain what some of these boxes are doing in more detail:

  • Catapult Design Checker – uncover coding bugs using static and formal approaches.
  • Catapult Coverage – C++ coverage analysis, knowing about hardware.
  • Assertion Synthesis – auto-generation of assertions in the RTL.
  • SCVerify – creates a smoke test, and sets up co-simulation of C++ and RTL, comparing for differences.
  • Questa CoverCheck – finds unreachable code using form RTL coverage analysis

Checking C++ Code

So, this newer flow looks pretty automated, yet there can still be issues. For example the C++ is untimed, while RTL has a notion of clock cycles, so during RTL simulation it’s possible for a mismatch to arise. The Catapult Design Checker comes into play here, and when run on several Konica Minolta designs the tool detected some 20 violations of the Array Bound Read (ABR) rule, where an array index is out of bounds. Here’s an ABR violation example:

The fix to this is adding assertions in the C++ code:

With the C++ assertions in place you will see any violations during simulation, plus Assertion Synthesis will add PSL code as shown below that are used during RTL testing.

Code Coverage

The Catapult Coverage (CCOV) tool understands hardware, while the original GCOV tool doesn’t, so CCOV supports coverage of:

  • Statement
  • Branch
  • Focused Expression
  • Index Range
  • Toggle Coverage

One big question remains though, how close is C++ coverage to the actual RTL coverage? The SCVerify tool was used on 10 designs to compare results of statement and branch coverage, which shows close correlation below with an average statement coverage of 97% and branch coverage of 93% for CCOV.

Unreachable Code

Having any unreachable code is an issue, so using the Questa CoverCheck tool helps to identify and then selectively remove if from the Unified Coverage Database (UCDB). Here’s what an engineer would see after running CoverCheck, the items shown in Yellow are unreachable:

Once a designer sees the unreachable code they decide if this was a real bug or can be waived, if the element is reachable then create a new test for it.

Closing Coverage

During high-level verification the LSI engineers are trying to reach coverage goals, and they can ask the algorithm developers to add more tests. In the future the algorithm developers could use CCOV to reach code coverage, while the LSI engineers use the remaining Catapult tools to reach RTL closure.

Conclusions

Takashi Kawabe’s team at Konica Minolta have successfully been using Catapult tools in a C++ flow over the years to more rapidly bring products to market than with traditional RTL entry methods. By using the full suite of Catapult tools they are simulating 100X faster in C++ than at the RTL level, and have shown that C++ level signoff is now possible.

The design world has come a long way since the 1970’s, and using C++ level design and verification is here to stay.  There’s an 11 page White Paper authored by Kawabe-san on this topic, and you can download it online here.

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WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation

WEBINAR: GPU-Powered SPICE – The Way Forward for Analog Simulation
by Randy Smith on 07-10-2019 at 9:37 am
Categories: EDA, Empyrean, Events

Several years ago, I was a consultant to a company called Gauda, Inc.  I enjoyed working with Gauda as the technology was interesting. On June 3, 2014, Gauda, Inc. was acquired by D2S, Inc. so their technology lives on. Gauda was focused on optical proximity correction (OPC) and optical proximity verification solutions utilizing GPUs, rather than CPUs, as the main processing engine. To do this, one must excel in parallelizing computationally intense algorithms and then properly map those algorithms onto the very different architecture of a GPU. It seems that Empyrean has been able to do this in order to produce a GPU-powered SPICE simulator. I am really interested to learn more about Empyrean’s approach and results and now we will all get the chance to do just that!

 

On August 8th, 2019 at 10:00 am PDT, Empyrean will discuss ALPS-GT™, the EDA industry’s first commercial   GPU-Powered SPICE simulator during a SemiWiki Webinar Series event. ALPS-GT has already been adopted by some top SOC design houses. The discussion will be led by Chen Zhao of Empyrean. Chen will provide concrete comparative numbers on some of the most challenging designs against Empyrean’s own traditional CPU-driven ALPS™, which was voted by users as the “Best of DAC 2018” in SPICE simulation for performance (3X to 8X faster than other industry-standard parallel SPICE simulators for post-layout simulation in 2018). ALPS and ALPS-GT together cover a large pool of users and types of designs. ALPS-GT was showcased at DAC 2019 and received lots of attention. Empyrean has been working closely with some key, early customers in the use of ALPS-GT for several designs in the 7nm process technology node and seem to now be ready for the broader market.

Chen Zhao is an application engineering manager of Empyrean Software. He is responsible for application engineering and customer support since he joined Empyrean in 2014. Zhao has extensive experience in full custom IC design and SPICE simulation. Zhao received a BS degree in electrical engineering from New York University and an MS degree in electrical and computer engineering from Johns Hopkins University.

This webinar is the first in this year’s SemiWiki Webinar Series which is anticipated to have many more webinars this year. Each webinar is expected to last between 30 and 45 minutes. There will be a brief introduction, followed by 20-to-30 minutes of technical presentation and/or demonstrations, followed by a Q&A period. As we expect many attendees, we may not get to all questions during the webinars, but we will be sure to ask the presenting companies to get back to you by phone or email to answer all your questions. I will be moderating many of these webinars which are expected to be quite informative in showcasing the latest developments in EDA, semiconductor IP, and related markets.

Click here to register for this webinar. Once registered, you will also receive a few reminders.

About Empyrean Software
Founded in 2009, Empyrean Software is an Electronic Design Automation (EDA) and intellectual property (IP) technology leader delivering fast and true physically aware, design closure and optimization solutions for timing, clock and power of systems on chip (SoCs). The company also offers a high-performance accurate circuit simulator and is an analog IP and fast SerDes IP provider. For details, go to http://www.empyrean-tech.com/

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Smart Hearing is Heating Up

Smart Hearing is Heating Up
by Bernard Murphy on 07-10-2019 at 6:00 am
Categories: AI, Cadence, IP
3 Comments

A lot of the attention in intelligent systems is on object detection in still or video images but there’s another very active area, in smart audio. Amazon and Google smart speakers may be the best-known applications but there are more obvious (and perhaps less novelty-driven) applications in enhancing the hearing devices we already use, in headphones, earpods and hearing aids, also in adding voice-control as a new dimension to human/machine interfaces.

Knowles IA8201

I talked to Jim Steele, VP of technology strategy at Knowles, a company that may not be very familiar to my readers. Knowles has been working in the audio space for around 70 years and is now addressing mobile, hearable and IoT markets. They provide for example microphones and smart microphones, audio processors, and components for hearing aids and earpods. They’re inside the Amazon Echo, cellphones and many hearing aids. Not surprising that they claim “Knowles inside” for many audio experiences.

About 4 years ago, Knowles acquired Audience, a company that specialized in mobile voice and audio processing. Audience was already used in a number of brand-name mobile phones and was apparently the first proponent for using multiple microphones together with auditory intelligence (I would guess beamforming, acoustic echo cancellation [AEC], etc.) to suppress background interference in noisy environments. Combining Knowles and Audience technologies provided a pretty rich set of capabilities which they recently spun into their IA8201 chip, the latest product in their AISonic family of audio edge processors. This is a variant on their IA8508 core, right-sized especially for ultra-low power always-on applications with trigger-word detection.

The design (block diagram pictured above) is based on three Tensilica cores, adapted with Knowles customization. The DeltaMax (DMX) core does the heavy lifting in beamforming, AEC, barge-in (you want to give a command while music is playing), noise suppression and multiple other functions. The HemiDelta handles ultra-low power wake-word detection and the Tensilica HiFi 3 core provides audio and voice post processing for leveling, equalization and other functions.

There’s a lot of technology here packed into a small space. This device supports up to 4 microphones which, together with beamforming and other features, should provide excellent speaker discrimination in most environments. This will be a real boon for the hard of hearing (yes, there are already hearing aids on the market with multiple microphones in each device).

Trigger-word detection can be as low as 1-2mW, allowing for extended use between charges. Certainly useful for a battery operated smart-speaker, but also useful for using your earbuds to make a call through a Bluetooth connection to your phone. Just say “Hey Siri, call my office”. Barge-in lets the command through, the trigger word is recognized and microphones in the earbuds pick up your voice through bone conduction (sounds creepy but that’s the way it works).

Voice recognition for command-processing runs on the DMX code, through temporal acceleration via 16-way SIMD with an instruction set optimized for machine-learning. Wake-word training can be supported by Knowles for OEMs and user-based training is also supported for command words and phrases.

Jim added that applications are not just about voice-support. A growing area of interest in products in this area is for contextual awareness: listening for significant sounds like sirens (while you’re driving – maybe you need to pull over), a baby crying, a dog barking or glass breaking (while you’re not at home). All of these can provide important alert signals. Of course you don’t want to be bothered with false alarms. Jim said that false accepts are down to 1 in 100 (for wake-word also) and can improve with training. Also alarm-type signals, OEMs might send video snip with the alert to help quickly determine if there is cause for further action.

Jim sees a lot of applications for this device, for hearables, for home safety and for IoT voice-control applications in appliances, TVs and other home automation devices. Lots of opportunity to get away from annoying control panels or phone apps, rather moving right to the way we want to control these devices – through direct commands. You can learn more HERE.

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The Nanometrics – Rudolph Technology Merger: What Was Nanometrics Thinking?

The Nanometrics – Rudolph Technology Merger: What Was Nanometrics Thinking?
by Robert Castellano on 07-09-2019 at 10:00 am
Categories: Information Network, Semiconductor Services
2 Comments

On June 24, 2019, Nanometrics and Rudolph Technology announced they will combine in an all-stock merger of equals transaction. The companies say the combination increases the SAM (served available market) opportunity to approximately $3B.

This article attempts to analyze the two companies in their different business segments, to compare these companies against their peers, and ascertain the validity of the claim that the SAM will increase by $3B. Finally, I will attempt to show that this merger is a mistake for NANO.

Financial Parameters

Table 1 shows financial parameters for NANO and RTEC between 2013 and 2018. Revenues for both companies are for ONLY the metrology/inspection market where both compete, so I deleted RTEC’s revenues coming from other areas such a lithography. This table also compares their revenues with the global wafer front end (WFE) market, so I eliminated RTEC’s back end metrology/inspection revenues. I will discuss these markets later in this article.

Of note is that these companies had revenues that are extremely small compared to the entire WFE market of $57.3B in 2018. As a percentage of revenue compared to WFE, NANO was never greater than 0.50% of WFE and RTEC never greater than 0.26%.

In Chart 1, I plot YoY growth of revenues listed in Table 1. NANO (orange) beat the WFE ((blue)) in three out of the five years while RTEC (grey) beat WFE on only two of five years.

Equally important, the WFE average YoY growth was 15.2%. This compares to NANO’s average five year growth of 21.8%, while RTEC has been erratic with an average five year growth of just 0.9%.

Metrology/Inspection Metrics

Metrology/inspection equipment is critical to assuring high yields in semiconductor manufacturing while acting as an alarm if processing conditions go out of sync and result in defective chips.

Chart 2 shows that market share for these companies is almost at the noise level of the $6B market, according to our report “Metrology, Inspection, and Process Control in VLSI Manufacturing.” Factor in KLA with a 50% share, and Hitachi High Tech and Applied Materials with 10% each, and it is implausible for this merged NANO-RTEC to increase its SAM in the overall metrology/inspection market.

We can hone in on various segments of the metrology/inspection market to see if these companies have a leading market share. Chart 3 shows that in the Wafer Inspection market, which makes up about 50% of the total metrology/inspection market according to our report. NANO is not a participant in this segment and RTEC held only a 1% share on revenues of just $30.6M

Chart 4 presents market shares for the Thin Film Metrology segment, which is about $1B. In this case, RTEC has a share in the noise level, but NANO held a 27.9% share in 2018. Here, NANO had a positive revenue increase of 28.1% YoY in 2018, based on sales of equipment to China for 3D NAND production. But in this segment, KLAC is a dominant player with nearly a 50% share, which will make it difficult for NANO to gain more share in 2019.

Advanced Packaging Market

RTEC sells both inspection and lithography equipment for advanced packaging of semiconductor devices. I refer the reader to my June 24, 2019 SemiWiki article entitled “Lithography For Advanced Packaging Equipment.” Chart 5 shows that although RTEC held a 28% share of the market in 2018, YoY its revenues grew only 10.0% compared to competitors, which grew 2-4 times greater. This subsegment is less than $400 million.

Lithography For Advanced Packaging Equipment

I presented in the above SemiWiki article my forecast that the advanced packaging market, primarily WLP, will grow at a compound annual growth rate of only 6.8% between 2016 and 2022, yes 2022 which is important as I’ll explain later. In the article, I also noted:

“The top three companies – Canon, Veeco, and EV Group held a 70% share of the market, and if we include SUSS, these companies held an 85% share of the market.”

RTEC is not included in the top four companies and NANO is not a participant in the market.

Flat Panel Display (FPD) Market

RTEC sells lithography equipment for flat panel displays. Unfortunately, the market for displays is dominated by Canon (CAJ) and Nikon (OTCPK:NINOY). Table 2 presents a forecast of FPD lithography equipment shipments. According to our report entitled “OLED and LCD Markets: Technology, Directions, and Market Analysis,” shipments in 2019 are forecast to drop 50% YoY and grow only 22% in 2020.

Lithography equipment for 10.5G panels (for TVs) are will represent nearly 50% of shipments in 2019 and 2020, and RTEC does not make a system that large. Equipment for 8G panels (for TVs) will be next, and RTEC also doesn’t make a system that large. RTEC’s focus is 6G for smartphones (a flat market) and microdisplays, although a nascent industry, is led by EV Group with its nanoimprint technology.

Takeaway

According to the NANO-RTEC press release:

“Each company currently has a semiconductor industry SAM of at least $1B, with additional SAM expansion opportunities of $400M to $500M per company. The combination is expected to expand the companies’ served market opportunity to approximately $3B.”

Thus, the press release spins the SAM to $3B, but no time frame is given. I expect little or no SAM growth in the Inspection/Metrology market for NANO-RTEC. For advanced packaging inspection and lithography (as discussed in my above SA article), a CAGR of 6.8% between 2016 and 2022 implies the advanced packaging market will only increase 40% between 2019 and 2022, significantly less than the 300% indicated for the SAM to increase from $1B to $3B.

In my opinion, NANO made a mistake in this merger. It has a larger market share than RTEC in Metrology/Inspection. NANO would be better served by acquiring or investing in metrology/inspection startups, thereby entering different segments of the market and thereby increasing its own SAM. In a December 31, 2018 SemiWiki article I noted:

“There are several startups gearing to compete against market leader KLAC. FemtoMetrix (Irvine, CA), uses Optical Second Harmonic Generation (SHG), a non-destructive, contactless, optical characterization method to characterize surfaces, interfaces, thin-films, as well as bulk properties of materials. Already, FemtoMetrix has completed its first round of equity financing in a deal led by Samsung’s Venture Division and SK Hynix Ventures, and announced a license agreement with Boeing. This type of new technology will eventually compete against KLA-Tencor.”

Semiconductor Metrology Inspection Outpacing Overall Equipment Market in 2018

RTEC has invested in a lot of applications, but they are in my opinion drilling 12 one-inch holes rather than one 12-inch hole, and as a result has minimal market share in markets led by large companies already firmly entrenched.

RTEC has a smaller market share than NANO in their core metrology/inspection market. So, another surprise is why the RTEC CEO will become the NANO-RTEC CEO.

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Automotive Market Pushing Test Tool Capabilities

Automotive Market Pushing Test Tool Capabilities
by Tom Simon on 07-09-2019 at 8:00 am
Categories: Automotive, Siemens EDA

It’s easy to imagine that the main impetus for automotive electronics safety standards like ISO 26262 is the emergence of autonomous driving technology. However, even cars that do not offer this capability rely heavily on electronics for many critical systems. These include engine control, braking, crash sensors, and stability and traction control. A failure of any of these systems can endanger human life or safety. As a result, there is a focus on implementing ISO 26262 across the board in products aimed at the automotive market. At the same time there is increasing complexity in many chips coupled with utilization of more advanced nodes, both of which have major implications for safety.

Meeting the requirements of ISO 26262 includes activity at every stage of chip development, starting during specification and going right through to design, manufacture, test and out into the field. Test in particular plays a significant role in implementing ISO 26262. After all, failure detection is essential. I recently had the opportunity to read an interesting white paper by Mentor on how their Tessent test tools can be helpful in meeting ISO 26262 requirements. The paper talks about three areas where test has evolved to meet the needs of ISO 26262 in the automotive market. They are on-line testing during chip and system operation, new types of testing to comprehensively detect a wider range of failures and making analog circuits testable.

Beyond just testing chips at the time of manufacture, or perhaps at power-on, ISO 26262 calls for continuous and periodic testing. Fortunately, many pieces of the manufacturing test elements embedded in the chip can be used for testing during operation. Mentor’s Tessent MissionMode architecture provides test access to individual IP and memory elements during chip operation. Tessent MissionMode in turn can be driven by previously stored test vectors or externally through the system bus. IEEE 1687 IJTAG is used to wrap IP blocks for test and can be accessed by Tessent Mission Mode. However, Tessent MissionMode can also access any other type of test interface, as needed.

One intriguing capability of Tessent MissionMode is non-destructive memory BIST. Testing is done in short busts, accessing small ranges of memory. This is non-destructive because the memory contents are saved and restored, making the test operation transparent to the running system. Because of the low overhead of each individual burst, this testing can cover the entire memory piecewise without contention with system operation.

Mentor also has some innovations in Logic BIST, where they apply a hybrid solution that utilizes ATPG and compression in Logic BIST, which can be used during power-on, power-off or for on-line testing. The benefits of this hybrid approach include area savings, because the scan chains are utilized for tester runs and self-testing. An issue with BIST during functional operation is increased power consumption due to high toggle rates. Tessent offers the ability to scale toggle rates to limit transitions, trading this off with some increase in pattern count.

The Mentor paper on Tessent also discusses how test methodologies have to move beyond ‘netlist’ level faults and add checking for cell level issues. The paper says that by some estimates cell level faults account for almost half of all circuit level defects. Traditional fault models are not targeting these faults. This means that many of these defects are found only by chance. Tessent now includes a Cell-aware methodology that digs deeper into the circuits to look for these harder to find defects.

Despite the well-established methodologies for digital fault analysis, analog designs have gone without until now. Tessent DefectSimfault simulator is the first commercial solution for analog designs. A key enabler is the development of analog simulation tools that run orders of magnitudes faster than before. It is now possible to efficiently look at parametric variations to help find defects. The paper describes some interesting techniques that are being applied to make analog test more effective. A majority of field failures in mixed signal chips occur due to issues with the analog portion. Automated analog test generation will be a tremendous help in securing ISO2626 compliance in mixed signal chips.

With every innovation in chip design, there comes an added challenge for test. The added requirements for meeting ISO 26262 add even more difficulty in the test domain. However, this Mentor white paper on the topic of how Tessent features can be applied shows that with innovation the test challenges for automotive systems can be more easily addressed. It also points out once again how the demands of developing automotive electronics is providing motivation for many of the current improvements in electronic design. The full white paper, entitled “MEETING ISO 26262 REQUIREMENTS USING TESSENT IC TEST SOLUTIONS” makes good reading and is easily available from the Mentor website.