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Could Trump Slump Give Mobility a Bump?

Could Trump Slump Give Mobility a Bump?
by Roger C. Lanctot on 07-21-2019 at 6:00 am
Categories: Automotive

Reports from Reuters last week suggested that the European Union member states “should brace for U.S. tariffs on several fronts in the coming months,” based on the comments of a senior German official who had met with “U.S. officials and lawmakers” in Washington. Among other sectors in the Trump Administration’s crosshairs vis-a-vis the EU was automobiles.

https://tinyurl.com/y2y58yfp – “Europe Should Brace for Tariffs on Several Fronts – German Official” – Reuters

This was only the latest twist in the ongoing automotive industry disruption emanating from Washington, which has coincided with a global downturn in vehicle sales – as reflected in recent reports from LMC Automotive and other industry forecasters. While LMC and its peers lay the blame for the decline on many causes, including changing emissions regulations in China, the largest global auto market, the Trump Administration factors into diminished growth calculations alongside Brexit and softness in demand elsewhere in Asia.

Some analysts also perceive a hit to vehicle sales arising from signs of declining vehicle ownership in both developed and developing markets – as consumers shift their dollars away from the expensive proposition of owning cars. It’s too early to say for sure, but a collateral outcome of tariff-based warfare between the U.S. and the rest of the world could stimulate mobility services like ride hailing and car sharing. It is easy to see how in China, Russia, Africa and Latin America, companies such as DiDi, Yandex and Uber are presenting a very real alternative to car ownership.

To be sure, forecasters have been reducing forecasted sales volumes for cars on an annual basis for several years. The latest adjustments, however, reflect a more dramatic downturn signaling an overall decline while also becoming something of a self-fulfilling prophecy: the market looks like it is declining, so the industry prepares for that decline.

One thing the Trump Administration has indisputably introduced into auto makers’ planning is a huge helping of uncertainty. Threats of import tariffs have stalled production and plant construction plans in the U.S. for some importers. And they have failed, in the short term, to stem auto industry job losses or stimulate hiring.

In effect, the ongoing confrontations over imports with China, Japan, Canada, Mexico, and the E.U. have frozen auto makers like deer in the headlights. At a time when the industry is in desperate need of maximum flexibility and nimbleness to respond to rapidly changing technology, the Trump Administration has instituted a global condition of strategic vapor-lock. Auto makers simply don’t know how matters beyond their control will sort out in the short or the long run.

This uncertainty is now telegraphed throughout the entire supply chain. Major suppliers to the auto industry are more than 12 months into their efforts to shift production away from tariff-impacted sources, if waivers can not be obtained. The global downturn has one certain impact, which is to shave off several percentage points of market growth – while threatening to take growth entirely off the table.

So car makers reduce their production targets. Suppliers reduce their expectations. Investment in plants, equipment and personnel are stalled. Progress comes to a standstill.

Trump’s slump?

Is this Trump’s slump? That might be going too far to conclude. One thing is clear, though. The auto industry and investors have little tolerance for uncertainty. In the current uncertain environment, the only certainty is uncertainty. That is not good for any car company, regardless of where they make or sell their cars.

Another certainty is at risk in this equation. The automotive industry was once a reliable source of unmitigated growth thanks to steady demand in developed markets and growing demand from the developing world. That, too, is in question as mobility alternatives (ride hailing, car sharing) emerge in the developing world as an alternative to vehicle ownership and as developed countries use rules and congestion charges to limit access of privately owned vehicles to city centers. The trade wars of the Trump slump may actually end up giving a bump to mobility operators. While it may be good news – MAYBE – for mobility operators, it will be a bitter pill to swallow for auto makers.

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5G Faith & the Automotive Industry

5G Faith & the Automotive Industry
by Roger C. Lanctot on 07-19-2019 at 6:00 am
Categories: 5G, Automotive

As the automotive industry slowly comes to terms with the implications of 5G connections in cars there are few outside the industry that understand the significance of this technology transition. It isn’t just a technology turning point. It is an emotional turning point for the industry as well.

Announcements are beginning to appear from telematics suppliers such as Harman International regarding program wins for 5G hardware – modules and antennas – indicating that 5G is indeed coming to embedded automotive connections. This kind of news arrives even as 5G skeptics express their concerns regarding radiation, wireless network coverage and the need for thousands of micro-cells, and the varying allocation of spectrum around the world.

It’s a clear case of ready-or-not, here it comes! For car makers it is a case of deja vu all over again. There lies the rub. Wireless carriers giveth and wireless carriers taketh away.

Wireless carriers brought the automotive industry low speed, analog 2G connections. Years later those analog networks were replaced by incompatible digital systems disconnecting hundreds of thousands of connected vehicles with automatic crash notification applications. It was years before the impacted car companies had resolved the resulting class action law suits in the U.S.

Within the past two years AT&T in the U.S. shut down its 2G network, once again impacting multiple auto makers, many of whom offered their formerly connected customers aftermarket hardware upgrades. The onset of 5G raises the specter of network transitions once again.

The issue boils down to the fact that wireless carriers simply don’t understand car companies. Conversely, auto makers tend to hate wireless carriers. One measure of the disconnect between wireless carriers and car companies is the fact that many wireless carriers talk about connected cars as being part of the Internet-of-things (IoT) universe.

IoT in the wireless industry is code for low bandwidth applications – sometimes referred to as M2M – machine-to-machine. The IoT world, though, is dominated and characterized by monitoring or diagnostic systems. Automobiles are on the cusp of becoming some of the highest bandwidth using devices on the planet – with the exception of video streamers.

Connected cars are poised to become quite lively users of wireless connectivity. Few wireless carriers are preparing properly for a world where connected cars are not only the largest source of new device connections – a reality that has existed globally for the past few years – but also some of the most intense consumers of bandwidth. That is the real revolution that is sneaking up – not so slowly – on both the wireless and automotive industries. It is also a reason for the introduction of 5G – existing wireless demand is straining capacity.

The fact that the auto industry and wireless carriers have come together under the auspices of the 5G Automotive Association – a 120-member organization spanning carriers, car companies, infrastructure, semiconductor and hardware providers – to sort out technical issues and standards for 5G implementation is a monumental turn for the industry. But one question remains, even as car makers are suspending their disbelief and committing to 5G: This time around, can the wireless carriers make a truly long-term commitment to this latest network architecture – preserving forward compatibility… indefinitely?

The depth of historical frustration and jaded skepticism among long-time automotive engineers as to the reliability of wireless carrier promises is difficult to plumb. The fact that so many have already taken the plunge and begun baking in their 5G plans with all of the technical challenges yet to be overcome is a testament to their fortitude and faith.

Car makers, with few exceptions, are embracing the 5G revolution. That revolution promises to enable and support autonomous vehicles and new, transformative crash avoidance technology while opening the door to richer infotainment experiences in cars. There is no doubt, though, that the adoption of 5G in the automotive industry is a massive leap of faith with fingers crossed in corporate boardrooms from Munich and Stuttgart to Detroit, Tokyo, Seoul, and Shanghai. Hopefully, the industry will avoid a Charlie Brown moment this time around.

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Chapter 2 – Constants of the Semiconductor Industry

Chapter 2 – Constants of the Semiconductor Industry
by Wally Rhines on 07-19-2019 at 6:00 am
Categories: Wally Rhines
3 Comments

In the mid 1980’s, Tommy George, then President of Motorola’s Semiconductor Sector, pointed out to me that the semiconductor revenue per unit area had been a constant throughout the history of the industry including the period when germanium transistors made up a large share of semiconductor revenue.  I began tracking the numbers at that time and continue to do so today.  So far, it’s still approximately true.  If you are making a decision about a capital investment in semiconductor manufacturing, or even an investment decision for the development of a new device, this is a remarkably useful parameter to test the wisdom of your investment.  Figure 1 shows revenue per unit area data for the last twenty-five years (since I didn’t keep my records before that time). There are many possible explanations for why this empirical observation should be approximately correct. One of those explanations is the fact that semiconductor revenue and semiconductor manufacturing equipment costs, materials, chemicals and even EDA software costs all follow learning curves based upon the number of transistors cumulatively produced through history. Semiconductor revenue follows a learning curve that is parallel to the learning curves for all input costs to the design and production of semiconductors and is decreasing on a per transistor basis by more than 30% per year (FIGURES 2 through 6). The cost per transistor and the cost to process a fixed area of silicon therefore decrease at a constant rate with the same slope which is also the same decreasing slope as the revenue per transistor. The ratio between revenue and area therefore stays approximately the same.

Figure 1.  Revenue per unit area of silicon or germanium has been a long term constant of the semiconductor industry

FIGURE 2 provides another observation that most customers of electronic design automation (EDA) software find surprising. I’ve found that most EDA customers think that the EDA industry charges too much for its software and doesn’t feel the same pressure to reduce costs that is felt by its customers, the providers of chips. The learning curve for EDA software refutes this. The number of transistors sold by the semiconductor industry is a published number each year. So is the total revenue of the semiconductor industry and the EDA industry. When the EDA total available market (TAM) is divided by the number of transistors produced, we obtain the EDA software cost per transistor. This then shows that the EDA industry is reducing the cost of its products at the same rate as the semiconductor industry. That is as it must be. If the EDA industry doesn’t keep its learning curve parallel to the semiconductor industry learning curve, then the cost of EDA software as a percent of semiconductor revenue would increase and there would have to be cost reductions elsewhere in the semiconductor supply chain to offset it. As it is, EDA software costs are about 2% of worldwide semiconductor revenue (FIGURE 7) and this percentage has been relatively constant for the last twenty-five years.  This is also a fixed percentage of worldwide semiconductor research and development (FIGURE 8) which has been a relatively constant 14% for more than thirty years.

FIGURE 2.  Learning curve for transistors and EDA software

FIGURE 3.  Learning curve for front end fabrication equipment

FIGURE 4.  Learning curve for lithography and photomask making equipment

FIGURE 5.  Learning curve for semiconductor assembly equipment

FIGURE 6.  Learning curve for semiconductor automated test equipment

FIGURE 7. EDA revenue as a percent of semiconductor revenue

FIGURE 8. Semiconductor Research and Development as a percent of semiconductor industry revenue

Figure 9 shows the annual production of silicon measured by area.  This measurement follows a long term predictable curve.  Actual data moves above and below the trend line as companies over-invest in capacity when demand is strong and under-invest in periods of market weakness.  Investing counter-cyclically seems like a brilliant strategy but it’s very difficult to execute because semiconductor recessions force companies to squeeze capital budgets and to under-invest just when they should be investing.  Even so, this graph is useful because silicon area production is one thing that is predictable at least one year ahead.  We know approximately how much silicon area the existing wafer fabs are capable of producing and we are aware of the new wafer fabs that will be starting production in the coming year.  Wafer fabs that are pulled out of service are a small percentage of the total, especially during strong market periods, so next year’s silicon area is known fairly accurately.  Since market demand is not known, shortages and periods of excess capacity lead to magnified price changes as the capacity grows monotonically. But the growth or decrease of revenue in the coming year tends to be predictable when market supply and demand are reasonably balanced.  We know the revenue per unit area of silicon.  We also  know the area of silicon that will be produced next year.  Multiplying these two numbers gives us the revenue for next year.  That’s a useful number. Figure 10 shows how the annual semiconductor revenue correlates with a calculation based upon silicon area multiplied by the predicted ratio of revenue per unit area of silicon.  I find the correlation to be both remarkable and very useful.

Figure 9.  Area of silicon produced each year

FIGURE 10. Integrated circuit revenue vs calculation from silicon area and the revenue per unit area ratio

Semiconductor units shipped per year is also predictable (Figure 11).  This data from VLSI Technology covers the period since 1994.  While modest deviations do occur in years of severe recession or accelerated recovery, the long term trend is apparent and predictable. If you are purchasing capital for the long term, especially for assembly and test equipment, this data is particularly useful. Unit volume served as a cornerstone of semiconductor forecasts at the time I joined the industry in 1972. As far as I know, the unit volume had grown every MONTH since the start of the industry and it continued to do so until December of 1974 when the oil shock caused implosion of the market and semiconductor volume fell precipitously.

FIGURE 11. Integrated circuit annual unit volume of sales

One of the most common errors in semiconductor forecasting occurs when forecasters look only at revenue, ignoring the variability of price in the long term trend.  The unit volume is stable and predictable but the price is not. At the Symposium on VLSI Technology in Hawaii in 1990, Gordon Moore and Jack Kilby were present and we all commiserated about the death of Bob Noyce (who was Chairman of SEMATECH at the time) the day before the conference started. Despite his grief, Gordon went ahead with his presentation the next day highlighting what might be referred to as Moore’s Second Law, although it never caught on (for good reason). Gordon graphed the average selling price (ASP) of semiconductor components over their lifetimes, especially memory components.  His conclusion was that semiconductor components that start out at higher prices will eventually cost $1.00.  Figure 13 shows the data since 1984.  While the current trend and the distant history suggest that Gordon may have been right, this trend reveals major interruptions, the most notable of which was the DRAM shortage that occurred when Windows ’95 was introduced in 1995.  That drove up ASP’s and we have been slowly trending down ever since then toward the $1.00 asymptote.  The $1.00 price point should never be reached because there will always be newer components coming into the market but Gordon’s hypothesis is certainly interesting if not compelling.

One more interesting statistic is the number of transistors produced per engineer each year (Figure 13).  This is a quasi-measure of design productivity that reflects both the growing number of transistors per chip as well as the increasing volume of chips that have been sold each year. By this measure, productivity has increased five orders of magnitude since 1985.

FIGURE 12.  Average selling prices (ASP’s) of semiconductor components

FIGURE 13.  Transistors produced per electronic engineer

Read the completed series

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Semicon West 2019 – Day 2

Semicon West 2019 – Day 2
by Scotten Jones on 07-18-2019 at 10:00 am
Categories: AI, FD-SOI, FinFET, Semiconductor Services, TechInsights

Tuesday July 9th was the first day the show floor was open at Semicon. The following is a summary of some announcements I attended and general observations.

AMAT Announcement

My day started with an Applied Materials (AMAT) briefing for press and analysts where they announced “the most sophisticated system they have ever released”.

There are two versions of the system, The Endura Clover system is targeted at MRAM and the Endura Pulse Impulse PVD system is targeted at PCRAM and ReRAM. The fact that AMAT has developed a platform specifically for these emerging memories really speaks to their potential in the market. MRAM for example is now available as embedded memory from Global Foundries, Intel, Samsung and TSMC. It is particularly useful at the edge where memory spends a 99% of the time in standby and MRAM is lower power than Flash and has no standby power draw. PCRAM and ReRAM are more targeted at the cloud.

MRAM requires stacks of 30+ layers with 10 different materials and layers only a few angstroms thick. The new Endura Clover has 7 deposition chambers and each chamber can deposit up to 5 materials with sub angstrom uniformity plus there is a pre clean and an oxidation chamber. A typical MRAM has a bottom electrode, a reference layer, an MgO barrier, a free layer and a top electrode.  The system offers heating to crystallize layers and cryogenic cooling for sharp interfaces, AMAT claims a +20% performance gain and greater than 100x better endurance. The critical MgO barrier is RF sputtered from a ceramic MgO target.

Figure 1. Applied Materials Endura® CloverTM MRAM PVD System. Photo courtesy of Applied Materials.

PCRAM has less layers but compound materials are very sensitive to contaminants. The Impulse PVD system is claimed to offer tight composition control with thickness and uniformity control.

Figure 2. Applied Materials Endura® ImpulseTM PVD System. Photo courtesy of Applied Materials.

The systems offer on-board metrology with a spectrograph with 1/100 nanometer resolution for on-die measurement in vacuum.

AMAT has 5 customers for the MRAM configuration and 8 customers for the PCRAM and ReRAM version. They are expecting a hundred million dollars in system business this year.

Touring the Show

I spent some time walking around the show and I thought it looked busy for the first day. One thing that struck this year is the the trend for the major equipment and materials companies to not have booths any more is continuing. Many years ago the major equipment manufacturers such as ASML, AMAT, TEL, Lam and KLA would have huge booths, they all stopped having booths years ago. The last two years I have seen less and less of the large materials companies on the show floor. Not sure what the long term impact will have on the show, there were certainly a lot of booths for the smaller companies. It may just reflect the industry consolidation to fewer – well know customers.

For an industry going through a down-turn I thought the mood was pretty good. I did talk to one person who thought the equipment companies were surprised by the downturn in capital equipment spending. Apparently, some of the companies geared up production assuming that last years spending levels would continue. Personally, I find this surprising, clearly Samsung spending over $20 billion dollars a year on capital wasn’t sustainable.

Leti-Fraunhofer Announcement

Tuesday afternoon Leti and Fraunhofer held a joint press conference to announce a new joint initiative.

The goal of the initiative is to work together on solutions for Neuromorphic computing. They want to achieve a hardware platform that is like open source for software while addressing trust, safety and security. In the US a lot of data goes into the cloud to be processed and people lose control over their data. In Europe there are a lot more regulations and people own their data. They see the need for AI to run at the edge so people can keep their data on local devices. For example medical data stays on your own device.

They looked at what each other can do and also Imec, they see Imec for FinFETs, Leti for FDSOI and Fraunhofer and Leti for 3D Packaging. “If FD12 can’t provide the compute power, look to combine FDSOI with FinFET with Imec”.

They are approaching this as an Air Bus kind of model and have Fraunhofer work with Imec and Leti and not duplicate what the others are doing. Although imec wasn’t present at the press conference they were present at the Leti-Fraunhofer technical symposium that night.

They want to find solutions to opportunities in the market. Other entities can join, it is “an open house built on strategy”.

They have gotten positive feedback from the European Commission and there may be national programs as well.

Figure 3. The Leti-Fraunhofer press conference. Pictured from left to right Emmanuel Sabonnadière (CEO of CEA-Leti, France), Patrick Bressler (Managing Director Fraunhofer Group for Microelectronics), and Jorg Amelung, Head of research for Fab Microelectronics (Germany) within the FMD group of Fraunhofer.

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Location Indoors: Bluetooth 5.1 Advances Accuracy

Location Indoors: Bluetooth 5.1 Advances Accuracy
by Bernard Murphy on 07-18-2019 at 5:00 am
Categories: Ceva, IoT, IP, Mobile
1 Comment

OK, so you’re in a giant mall, you want to find a store that sells gloves and you want to know how to get there. Or you’re in a supermarket and you need some obscure item, say capers, that doesn’t really fall under any of the main headings they post over the aisles. If you’re like most of us, certainly like me, this can be a frustrating experience. Modern stores know how to provide up-to-the-minute information, they provide wireless internet, usually, and we have our phones. But there’s been no way to provide the kind of service we take for granted with GPS – where is the thing I’m looking for and how to I get there? So we have to ask, or check mall maps, try to find the right store, try to figure out where we are on the map and try to figure out how we are oriented relative to the map. What is this, the Dark Ages?

Mega-mall

The problem for indoor positioning is that GPS is quite literally dark indoors; GPS devices can’t see satellites in those cases. That’s pretty limiting, not just to personal convenience but also to enhanced automation. In industry 4.0 we want to track assembly progress through a production line, or locate machines having problems – all indoors. In a hospital, nurses want to find a crash cart when a patient goes into cardiac arrest – also indoors. You can’t afford to waste time finding out where a cart was last left. Less dramatically (Paddy McWilliams, Engg Dir at CEVA gave me this one), where the *#!@ did I leave my left earbud (maybe down the side of the sofa)?

Helping find something in these cases is an example of indoor positioning services (IPS). Tracking something which will frequently move (such as the crash cart) is classified as real-time location services (RTLS) and Bluetooth beaconing is a major player in both spaces. When you consider the size of the GPS market and the scope for similar services indoors, it’s not surprising that the Bluetooth beacon market has been estimated at $58B by 2025.

A challenge for Bluetooth in this kind of application has been accuracy since location has been determined primarily by signal strength. This gives an indicator of distance but not direction, and triangulation to multiple sources doesn’t help much, given limited range and need to consider noise and multi-path effects. Wi-Fi with triangulation suffers from similar problems, also unpredictable latencies. Another technology, ultra-wideband (UWB), claims accuracy to centimeter levels but is expensive in cost and power and interference is a concern near critical equipment. Frankly most of the time, we don’t need that kind of location accuracy. Get me in the ballpark and I can find it from there.

Bluetooth is a strong contender for IPS and RTLS for multiple reasons. It’s already in every mobile phone and virtually every other kind of mobile device. It’s best in low power (especially in BLE) and low cost. This already makes it good bet for mass deployment. If only we could fix that accuracy problem. That’s what the Bluetooth SIG has delivered with the 5.1 release of the standard, adding angle-of-arrival (AoA) and angle-of-departure (AoD) detection. These add directional information to the distance estimate derived from signal strength, allowing location of a device to be calculated with much higher accuracy, to within tens of centimeters to a meter in everyday conditions. That’s good enough for me to find where the capers are.

Two methods for angle detection let a product developer choose the optimum IPS approach to be used for the target application; AoA is aimed at very low cost tracking tags with location calculations performed by the infrastructure system, whereas AoD allows the location calculations to be performed at the mobile device, allowing greater privacy for the user.

Bluetooth 5.1 IPS accuracy is a perfect match in smart manufacturing, healthcare, proximity services in retail, way-finding in airports, shopping malls, and hotels, for all of which, sub-meter accuracy should be just fine. And using an already widely-established standard seems like an obvious advantage in scaling to these levels of deployment.

For RTLS, adding angular to distance-based estimation can improve tracking of rapidly-moving objects so it becomes easier to track assets moving around a factory floor. RFID is the classic solution here but is obviously very short-range, where Bluetooth 5.1 can reach several 100m indoors, making (semi-)continuous monitoring much more practical.

Bluetooth 5.1 comes with some cost. The transmitter and/or receiver need an array of antennae to support angle-detection, depending on whether you want to support AoD or AoA methods. But this is modest compared to UWB and provides an opportunity for solution providers to add further differentiation to their products.

CEVA provides Bluetooth 5.1 compliant IP, for both BLE and Bluetooth Dual-Mode, under the RivieraWaves family, adding to its existing support for location services in GNSS and Wi-Fi-based location. Check them out next time you circle the supermarket three times trying to find those capers.

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Silvaco Talks Atoms to Systems – Where to Next?

Silvaco Talks Atoms to Systems – Where to Next?
by admin on 07-17-2019 at 10:00 am
Categories: EDA

At the ES Design West event in San Francisco last week Silvaco’s CTO and EVP of Products, Babak Taheri, gave a presentation titled, “Next Generation SoC Design: From Atoms to Systems”. The time slot for the talk was only 30-minutes which is simply not enough to discuss all the technology Silvaco is providing now. I had not looked closely at Silvaco in a while. I came away with a strong feeling that they are more like an iceberg – there is a lot beneath the surface, and their technology breadth is much more than most people realize. If you are not using them already, you probably should be.

It was only 3 years ago that Silvaco acquired IPextreme, launching the company’s semiconductor design IP portfolio. Silvaco’s breadth in IP now encompasses more than 100 production-proven IP cores and foundation IP libraries (e.g., I/O, standard cells, memories). With their business model, they will also help commercialize captive design IP from semiconductor companies, such as Samsung Foundry, and include the application of their unique IP fingerprinting technology.

Although all the technology areas are related to some extent, I view design IP as more of a “systems” product. What was intriguing me in the talk was the focus on “atoms”. Let’s face it, in the EDA world, even when EDA was called CAD, we always talked about systems. I don’t remember much discussion on atoms in semiconductor design since my last course in electromagnetic theory in college. Slide 8 of the presentation was titled “Design Technology Co-optimization (DTCO)”. It showed a Silvaco flow from the functions Process Simulation to Device Simulation to Automatic Parameter Extraction and into Circuit Simulation. There were some other cyclical pieces after that, but the first two boxes are what drew my attention. I worked at Celestry before it was acquired by Cadence and Celestry had significant TCAD business related to transistor modeling. So, what I think we must conclude from Babak’s message is that something important is changing here. All the new technologies which are evolving rapidly (MRAM, RRAM, advances in Flash and any other non-volatile memory technologies) taken together with feature sizes that can be measured in a few atoms demand that we rethink the approach to design. Masks are expensive; production is costly and time-consuming. New tools will be needed to make sure the silicon will function as intended. The first two boxes in the slide above were marked as Victory Process and Victory Device. A common platform of products related to process simulation and device simulation at the atomic level?

Apparently – Yes. Victory Process™ is a general purpose 1D, 2D and layout-driven 3D process simulator for applications including etching/deposition, implantation, annealing, and stress simulation. Victory Device™ enables device technology engineers to simulate the electrical, optical, chemical, and thermal behavior of semiconductor devices. Victory Device is physics-based and simulates in 2D and 3D using an advanced tetrahedral meshing engine for improved accuracy. Clearly, 3D simulation is a must for finFET technologies. In his talk, Babak mentioned the need for tools that contemplate a small number of atoms in some of the semiconductor structures. The base technology is all here at Silvaco, and if you are doing this type of work you should use it now. Still, what will be needed next? I am sure Silvaco is thinking about it.

About Dr. Babak Taheri
Babak Taheri is the CTO and EVP of products at Silvaco, a leading EDA Software Company. He manages the TCAD, EDA, and IP product divisions at Silvaco. Previously, he was the CEO / president of IBT working with investors, private equity firms, and startups on M&A, technology, and business diligence. He also held VP/GM roles at Cypress Semiconductors, Invensense (now TDK) and key roles at SRI International and Apple. He received his Ph.D. in biomedical engineering from UC Davis with majors in EECS and Neurosciences, has over 20 published articles and holds 28 issued patents.

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Semicon West was sluggish with hopes of 2020 recovery

Semicon West was sluggish with hopes of 2020 recovery
by Robert Maire on 07-17-2019 at 6:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

Bouncing along a not too bad bottom
Given that we have followed the semiconductor industry through many down cycles, we can safely say that this one isn’t all that bad by comparison. Everyone, big & small, is still safely profitable and in relatively good shape. Though we are seeing the normal week long holiday shut downs typical of the downcycle we are not seeing wholesale layoffs or cuts.  Its not all that painful (by comparison to past down cycles). While not busy and up beat , Semicon West was not the funeral we had experienced in past down turns.

The “new normal” will be different than the “old normal”
We think that when the industry does recover, it won’t be the rip snorting, maniacal memory spending we saw in the last up cycle. It will likely be more evenly balanced between memory and logic and we would not be surprised if logic/foundry led the way off the bottom rather than having a memory driven recovery.

There are likely those who would say that you can’t have a “real” recovery without memory (and we might be one of them…), but we could have some sort of recovery.

The past cycle was an almost perfect storm of memory spend, driven by the conversion from rotating media to SSDs, sucking up a tidal wave of NAND.  At the same time, the industry was going through a massive conversion from 2D planar memory to 3D NAND, buying equipment in leaps and bounds. We are now well past the bulk of the SSD conversion as well as virtually 100% of the 3D NAND conversion, those waves have washed over the industry and subsided very quickly as the tide went out following them.

Memory industry will be gun shy for a while-
Given the beating that memory pricing has taken we doubt that memory makers will jump back into spending with prior vigor.  Spending in memory will be much more measured and incremental. The need for huge spending to convert to 3D doesn’t exist anymore. We also already have enough capacity in the industry for current SSD consumption and then some, so we don’t need big spending for that either. In short, the need for big memory capex doesn’t exist as we are well past the SSD/3D hump…..so don’t hold your breath for it.

5G could push logic/ foundry to recover first
We have heard of some good expected ramping of 5G chips at TSMC and elsewhere over the next several months. 5G devices not only for phones but for infrastructure.  While Qualcomm may be driving the first wave of 5G, others will soon add to the mix. While this is likely not enough to bump up TSMC’s capex significantly given the weakness in overall chip demand, we none the less think it positively impacts demand for leading edge production equipment.

More importantly, this wave of new 5G related demand will likely happen prior to a memory recovery which seems a year or more off at the very least. All this suggests that foundry/logic could recover first and stronger than memory…

The equipment mix will be different in this cycle
If we see a more evenly driven recovery between memory and logic or logic recovers first as we suspect, those companies benefiting will be different than last cycle.  In addition the upcoming cycle will obviously have a more significant EUV component.

We will also likely see a shift away from US suppliers in the coming up cycle as China will find ways to avoid America like the plague. Multiple patterning and multiple layer 3D NAND will be a smaller percentage of spend.

The stocks
In general, we see little reason to buy the stocks now as there is no reason when the recovery is so far off, well into 2020 or beyond.  Its not like the stocks are cheap or have sold off recently.

We would be more selective and look for down drafts or other news or event driven opportunities.  We don’t see much of a potential for upside surprise in the current reporting season either.  We think the potential for investor impatience is higher in the near term.

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WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis

WEBINAR: Eliminating Hybrid Verification Barriers Through Test Suite Synthesis
by Randy Smith on 07-16-2019 at 10:00 am
Categories: Breker Verification Systems, EDA

 

I’ve been following the evolution of the verification space for a very long time including several stints consulting to formal verification companies. It has always been interesting to me to see how so many diverse verification techniques emerge and been used, but without much unification of the approaches. With the emergence and adoption of the Portable Stimulus Standard (PSS), we now have the chance to better unify these approaches in a more meaningful way.

The combined use of simulation and emulation in a verification flow is now commonplace. Many engineering groups have begun augmenting this combination with virtual platforms to create a fully hybrid verification process. This allows for increased capacity and performance, as well as a shift left approach to design architecture and test planning. One barrier remains to a seamless flow between these tools, the fact that each process component requires a different testbench format. Furthermore, improved test content application may significantly accelerate these individual processes.

This webinar will be held in three different time zones starting on August 13, 2019, in the United States,  and will discuss Test Suite Synthesis, where verification scenario intent is described using the new PSS and then synthesized to the respective process implementation. The white box intent description can be used to accelerate UVM block verification, Software Driven Verification (SDV) for SoCs, and prototyping and post-silicon validation, increasing quality while reducing schedules. In addition, this same test description can be used across all these processes, providing a continuous, back and forth flow across the entire verification process. During the webinar you will see a demonstration of the practical application of test suite synthesis on real designs as they progress from architecture to block to SoC, leveraging hybrid verification techniques.

The main portion of the webinar will be presented by Aileen Honess. Aileen has more than 20 years of experience teaching, mentoring, and leading hardware verification projects across a variety of disciplines, companies, and continents. She is an expert in UVM and has recently been assisting those who are modernizing their verification methodology by adopting portable stimulus and portable specifications. After a long career at Synopsys as a lead application specialist in verification, she has assumed the role of Technical Specialist at Breker Verification Systems. She holds a BS in Electrical Engineering from UCLA.

Click here to register for this webinar. Select your time zone to determine which webinar session best fits your schedule. Once registered, you will also receive a few reminders.

About Breker Verification Systems
Breker Verification Systems is the leading provider of Portable Stimulus solutions, a standard means to specify verification intent and behaviors reusable across target platforms. It is the first company to introduce graph-based verification and the synthesis of powerful test sets from abstract scenario models. Its Portable Stimulus suite of tools is Graph-based to make complex scenarios comprehensible, Portable, eliminating test redundancy across the verification process, and Shareable to foster team communication and reuse. Breker’s Intelligent Testbench suite of tools and apps allows the synthesis of high-coverage, powerful test cases for deployment into a variety of UVM to SoC verification environments. Breker is privately held and works with leading semiconductor companies worldwide. Visit www.brekersystems.com to learn more.

Also Read

Breker on PSS and UVM

Verification 3.0 Holds it First Innovation Summit

CEO Interview: Adnan Hamid of Breker Systems

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Safety Methods Meet Enterprise SSDs

Safety Methods Meet Enterprise SSDs
by Bernard Murphy on 07-16-2019 at 5:00 am
Categories: Arteris, IP

The use of safety-centric logic design techniques for automotive applications is now widely appreciated, but did you know that similar methods are gaining traction in the design of enterprise-level SSD controllers? In the never-ending optimization of datacenters, a lot attention is being paid to smart storage, offloading storage-related computation from servers to those storage systems. Together with rapid growth in SSD-based storage at the expense of HD-based storage (at least in some applications), this inevitably creates lots of new and exciting challenges. One consequence is that the controllers for SSD systems are now becoming some of the biggest and baddest in the SoC complexity hierarchy.

Why are these devices so complex? Certainly they have to offer huge bandwidth at very low latency (performance is a big plus for SSD) in architectures where a mother-chip controller may be managing multiple daughter controllers each managing a bank of SSDs. Datacenters have high cooling costs so expect low power (a big appeal for SSDs). And they also expect high reliability for enterprise applications; no-one would want to use a datacenter that loses or corrupts data. That last point is where the connection to safety-related design techniques comes up.

Then there’s lots of house-keeping, finding and isolation bad locations, sampling to predict and proactively swap out locations likely to fail, also needing to put aside un-erased blocks to be erased during quiet periods (since erasing is a slow process). All of this is known as garbage collection. On top of these functions, the controller can manage encryption, compression and lots of other offloadable features that don’t need to be managed by the server, for example SQL operations. At least that’s one viewpoint; there seem to be differing opinions on the pros and cons of offloading, see the link above.

But there’s no debate on the need for reliability. JEDEC defines a metric called Unrecoverable Bit Error Ratio (UBER) which is the number of data errors divided by the number of bits read.  Consumer-class SSDs allow for slightly less reliability, where occasional re-reads may not be too intrusive. But enterprises expect ultra-high reliability and a higher UBER, so more must be done in controllers to ensure this reliability. A lot of this is in proprietary hardware and software design to manage system aspects of reliability but some must also be basic functional reliability, demanding support in design methodologies and tools.

The need for reliability comes from the same concerns that we see in vehicles – cosmic ray events, EMI events and similar problems. These devices are all built in advanced processes and are just as vulnerable to these classes of problems as automotive devices. Which in turn means you want parity-checking, ECC for memories, duplication (or even triplication) and lockstep operation, all the design tricks you use to mitigate potential functional safety problems for ISO 26262.

Curiously, when Arteris IP first built the Resilience Package for their FlexNoC interconnect IP, their first customers were enterprise SSD builders, originally small guys, now consolidated into companies like WD, Seagate, Samsung, Toshiba and Intel. Over time, Arteris IP started to get more uptake among companies building for automotive applications thanks to growing adoption of the ISO 26262 standard. But SSD continues to be a driver; they’re now starting to see adoption in China for this kind of application.

In a lot of cases in an SoC design, safety mechanisms must be managed by the integrator, but in the interconnect, it is reasonable to expect that the IP generator should handle these reliability functions for you. This is what the FlexNoC Resilience package does. It also provides a safety controller to manage faults and a BIST module to continually monitor test data protection hardware during quiet periods. The Resilience package also natively supports the ECC and parity protection schemes used by the Cortex-R5 and R7 cores, unsurprisingly since these are the cores most commonly used in SSD controllers.

I should add that this support isn’t the only reason SSD controller designers use the Arteris IP interconnect solutions. Remember that these devices are some of the biggest, baddest SoCs around? That means the SoC-level connectivity at minimum has to be through NoC interconnect. Traditional crossbar fabrics would be simply too expensive in performance and area; only the NoC approach can guarantee the QoS demanded by these systems. Even large subsystems will depend on NoC fabrics for the same reason.

Kurt Shuler (VP Marketing at Arteris IP) tells me these approaches are now trickling down to consumer-grade SSD. I may only be a consumer, but I don’t like waiting for slow disk operations either. Can’t come too soon for me. You can learn more about this topic HERE.

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SEMICON West 2019 – Day 1 – Imec

SEMICON West 2019 – Day 1 – Imec
by Scotten Jones on 07-15-2019 at 10:00 am
Categories: Events, Lithography

On Monday, July 8th Imec held a technology forum ahead of Semicon West. I saw the papers presented and interviewed three of the authors. The following is a summary of what I feel are the keys points of their research.

Arnaud Furnemont
Arnaud Furnemont’s talk was titled “From Technology Scaling to System Optimization”. Simple 2D dimensional scaling has slowed. Design Technology Co-optimization (DTCO) has led to track height reduction but as track heights shrink it leads to fin depopulation and requires process optimization to maintain performance. DTCO and scaling continues to be important, but we need to also look from the top down as scaling from a system perspective using System Technology Co-Optimization (STCO).

As dimensions scale down a limit is eventually reached for each technology and a transitions from 2D to 3D is required. We have already seen this happen with 2D NAND transition to 3D NAND. For DRAM’s he sin’t convinced capacitor scaling continue below the D13/D14 nodes and a 3D solution is needed. 3D XPoint memory will need to increase the number of layers and logic will also have to transition to 3D.

Figure 1 summarizes half pitch limits for memory by technology.

Figure 1. Memory Scaling Limits.

For logic scaling there are opportunities to partition functions in an intelligent manner. Backside power delivery through thinned wafers with micro TSVs and separately fabricating SRAM and logic and then integrating them offer options for more highly optimized solutions, see figure 2.

Figure 2. Smart Partitioning.

I have previously written about backside power delivery here.

Naoto Horiguchi
Naoto Horiguchi gave a paper entitled “Vertical Device Options for CMOS Scaling”. The main point of the papers was that vertical devices could provide a shrink to SRAM arrays versus horizontal tarnsistors, see figure 3.

Figure 3. SRAM Shrink from Vertical Transistors.

This work fits in with the previous paper because by fabrication an SRAM only array the process scan be simplified versus a full logic process, for example SRAM only requires approximately 4 interconnect layers versus 12 or more for leading edge logic.

Figures 4 and 5 illustrates the basic process for a 5nm class vertical SRAM array. The process steps in blue are EUV layers (note that the Top Electrode is mot in blue but is also an EUV layer).

Figure 4. Vertical SRAM Array Front End Of Line (FEOL) Process.

Figure 5. Vertical SRAM Array Back End Of Line (BEOL) Process.

This work was also published at the VLSI Technology Forum [1] and between figures 4 and 5 and the VLSI paper the process becomes the process can be outlined in more detail.

  1. An N-type Epi layer is deposited.
  2. 2 noncritical masks and implants are used to fabricate high doped N and P wells.
  3. A 70nm thick P-type channel Epi layer is grown.
  4. An EUV mask and etch is used to form 8nm diameter nanowire pillars. The etch is 100nm deep etching down into the high doped wells.
  5. An EUV mask and etch is used to create isolating trenches between sets of pillars.
  6. The trench is filled and then an oxide recess etch is performed, this exposes the upper areas of the pillars for gate formation.
  7. A chemical oxidation is performed to create and interface oxide, this is followed by ALD depositions of HfO2 and TiN.
  8. A Tungsten (W) fill is now deposited, CMP planarized and then a recess etch is performed.
  9. An EUV mask and etch is performed to form the gates and then an oxide fill is performed.
  10. An EUV mask, etch and W fill is performed to create the bottom gate contact.
  11. An EUV mask, etch and W fill is performed to create cross couples.
  12. A barrier layer is deposited, masked and etched and then a selective epi of Si:B is grown to form the top source/drain for the PMOS.
  13. A barrier layer is deposited, masked and etched and then a selective epi of Si:P is grown to form the top source/drain for the NMOS. An oxide is then deposited.
  14. An EUV mask, etch and W fill is performed to create the top electrode. An ILD oxide layer is deposited and planarized.
  15. An EUV mask, etch and W fill is performed to create the gate contact.
  16. An EUV mask, etch and W fill is performed to create the top electrode contact.
  17. An oxide is deposited and planarized, an EUV mask and etch is used to create a metal 1 trench that is then filled with damascene copper.
  18. An EUV mask, etch and W fill is used to create a super via.
  19. EUV masks and etches are used to create metal 2 and via 2 and then they are filled with dual damascene copper.

This flow is used to create Vertical SRAM test devices. A full flow would include at least two more metal layers and likely some processing for ESD protection. This array could them be integrated with logic and backside power distribution as shown in figure 2.

Zsolt Tokei
Zsolt Tokei presented a paper entitle 3nm Interconnects and Beyond: A toolbox to Extend Interconnect Scaling”. In order to continue to scale down interconnect issue with resistance-capacitance (RC), cost, variability and mechanical stability need to be addressed. Figure 6 summarizes the path forward.

Figure 6. The Path Forward.

Conventional dual damascene and super vias for better routing give way to barrierless interconnect with air gaps possibly fabricated by semi-damscene. There is also research into integrated thin film transistor into the BEOL for increased functionality.

The semi-damascene is as follows:

  1. A via opening is patterned and etched in a dielectric film.
  2. The via is filled with Ruthenium (Ru) and Ru deposition continues until a layer of Ru is formed over the dielectric.
  3. The Ru is then masked and etched into metal lines.
  4. Air gaps are formed between the metal lines.

The Ru has a Titanium (adhesion layer) but the via to metal line interface is continuous Ru reducing resistance and the air gaps reduce the capacitance. Zsolt wouldn’t discuss the air gap formation process but presumably some kind of conformal film is deposited and then pinched off with another deposition.

This technique was used ot fabricate the world’s first 21nm pitch interconnects. Figure 7 summarizes the results.

Figure 7.  21nm Pitch Interconnect.

Figure 8 illustrates a thin film transistor (TFT) in the BEOL and describes some applications.

Figure 8. BEOL Thin Film Transistor.

Conclusion
Imec continues to produce cutting edge research to support continued scaling and improvements in semiconductor performance.

[1] M.-S. Kim, N. Harada, Y. Kikuchi, J. Boemmels, J. Mitard, T. Huynh-Bao, P. Matagne, Z. Ta1, , W. Li,
K. Devriendt, L.-A. Ragnarsson, C. Lorant, F. Sebaai, C. Porret, E. Rosseel, A. Dangol, D. Batuk,
G. Martinez-Alanis, J. Geypen, N. Jourda1, A. Sepulveda, H. Puliyalil, G. Jamieson, M. van der Veen, L. Teugels, Z. El-Mekki, E. Altamirano-Sanchez, Y. Li2, H.Nakamura, D. Mocuta, F. Masuoka, “12-EUV Layer Surrounding Gate Transistor (SGT) for Vertical 6-T SRAM: 5-nm-class Technology for Ultra-Density Logic Devices,” VLSIT Symposium (2019).