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SPIE Advanced Lithography Conference – Imec design papers

SPIE Advanced Lithography Conference – Imec design papers
by Scotten Jones on 06-27-2019 at 10:00 am

At the SPIE Advanced Lithography Conference Imec presented several design papers and I have had the opportunity to review the papers and speak with the authors. In this summary I am going to address three emerging areas in order of when I think they may be implemented from soonest to latest.

Specifically, I will discuss:

  1. Buried Power Rail (BPR)
  2. Backside Power Distribution
  3. Complementary FET (CFET)

Buried Power Rail

Logic designs are made up of standard cells. The size of a standard cell depends on metal pitch, cell track height, poly pitch and whether it is single or double diffusion break. For many years scaling was driven by metal pitch (MP) and poly pitch (PP) scaling, but MP scaling faces lithographic and resistance challenges and PP scaling has slowed due to device issues. The use of Design Technology Co-Optimization has led to track height scaling becoming a major scaling knob, but track height scaling also presents challenges.

Figure 1 shows scaling with a 40% per node area shrink goal.

Figure 1. Area scaling.

Scaling limitations also result in more restrictive design rules.

Figure 2 illustrates the evolution of designs by node.

Figure 2. Design evolution with node.

 From figure 2 it can be seen that as we have moved to smaller nodes 2D poly and metal layouts have given way to 1D layouts and more complex Middle Of Line (MOL) interconnect schemes.

Figure 3 presents the number of fins versus track height. The height of a cell is the MP multiplied by the number of tracks. As the MP and number of tracks are reduced there is less room for fins and fin depopulation is required.

Figure 3. Scaling challenges.

 As cell heights have scaled from 9, to 7.5, to 6.5 and eventually 5 tracks the number of fins per cell has been reduced from 4 to 3 to 2 and eventually 1 fin. This will also result in decreased drive current unless something is done to otherwise optimize the device.

Power rails for cells (Vdd and Vss) are typically some multiple of MP (see upper left in figure 3). At 5 tracks the spacing is so tight that in order to realize the cell the power rails must be moved out of the MOL interconnect layers and down into the substrate as Buried Power Rails (BPR). An illustration of BPR is presented in the CFET section.

BPR present fabrication and material challenges with the BPR having to survive subsequent high temperature transistor fabrication steps. The material used for the BPR has to be selected for low resistance and high thermal stability. One target material is Ruthenium but Ruthenium is very expensive.

 Backside Power Delivery

While BPR helps with the layout challenges to get to a 5-track cell, there are still issues with IR-drop due to the rising resistance of the very thin interconnect lines. Backside power delivery addresses these issues by creating large power distribution lines on the underside of the device and connecting them up to BPR using Micro Through Silicon Vias (µTSV).

Figure 4 illustrates the backside power delivery process flow.

 Figure 4. Backside Power Delivery process flow.

 The backside power delivery process flow begins with a wafer that has buried power rails.

  1. The wafer is temporarily bonded to a carrier wafer.
  2. Wafer thinning is performed.
  3. The backside passivation is patterned.
  4. High aspect ratio through silicon vias (TSV) are formed and filled.
  5. Backside power rails are formed.

The process requires extreme wafer thinning and precise location fo very small TSVs.

 Complementary FET (CFET)

The CFET concept is simple, instead of fabricating nFET and pFET devices next to each other they are stacked, see figure 5.

Figure 5. CFET scaling concept.

 As was discussed in the section on buried power rails as track height is scaled down fin depopulation occurs with a single fin expected for a 5 track cell.

The CFET design break the p to n separation distance bottle neck and can enable a 4 track cell height with 2 fins, see figure 6.

Figure 6. CFET scaling.

 Vertically stacking nFET and pFET devices creates and interconnect challenge and requires more complex middle of line (MOL) approaches. Figure 7 illustrates a 4 track cell in cross section and figure 8 illustrates a 3 track cell in cross section.

Figure 7. Cross section of 4 track CFET cell.

Figure 8. Cross section of 3 track CFET cell.

Finally, figure 9 summarizes the advantages of the CFET concept.

Figure 9. Benefits of a CFET.


The challenges of continued logic scaling are being met with innovative new process designs. Buried power rails and backside power distribution address power distribution requirements for low resistance in small areas.

CFETs present an opportunity to address horizontal scaling limits with a 3D logic approach.