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Layoffs à la Fairchild

Layoffs à la Fairchild
by John East on 07-01-2019 at 5:00 am
Categories: John East
5 Comments

The “20 Questions with John East” series continues

You wouldn’t think that layoffs would be a subject that I’d want to talk about in my stories of  “Silicon Valley the Way I saw it.”  The subject is just plain distasteful!!  — Still  — layoffs were a major part of the valley’s culture back in the day.  To give a true picture of how it felt to work at Fairchild in the early 70s, this story must be told.

When Les Hogan and his heroes joined Fairchild, Fairchild had been losing money. As I look back on it, I imagine they might have been in the middle of a cash crisis.  Also, in looking back it seems that there wouldn’t have been a quick fix.  TI clearly had a superior cost structure to ours.  Our wafer sort yields weren’t good at all and we didn’t have an inexpensive plastic package to match the one that TI had developed. The picture from the top couldn’t have been rosy. One day Les Hogan was interviewed by someone in the financial press.  He was asked what he intended to do to stem the losses. His answer,  “That’s not a problem. We’re going to reduce the headcount by a third. That will get our spending back in line.”

That quote made the front page of the business section of the local newspaper.  It probably felt good to the investors when they read it, but it felt really, really bad to the people who worked there.  That was not what we wanted to hear!  And that was the beginning of some serious layoffs.

Once they started, it seemed like every Friday somewhere in Fairchild there were layoffs. TGIF didn’t apply at Fairch!! Everyone would go straight to the cafeteria Friday mornings. No one bothered going to their desk. Everybody was scared to death. Everybody needed their job and knew that there was a very good chance that they would lose it in the next few minutes. Lots of gallows humor. Lots of camaraderie. Everybody loved everybody else. There are no atheists in foxholes.  And then, they started.

There was a very well known “journalist” who covered the semiconductor industry in those days.  His name was Don Hoefler. I never met Hoefler.  I think he had worked at Fairchild at one time and that there was bad blood when he left. Maybe he had been fired?  Maybe an “Off with their heads” casualty? He started writing a weekly industry newsletter. It was always very negative towards Fairchild. Needless to say, the upper echelon at Fairchild were not enamored of Hoefler. I heard several times that anyone caught in possession of one of Hoefler’s newsletters was subject to being fired   – but that might have been just a rumor.  After all, we all read it (being careful not to get caught) but so far as I know, no one was ever fired for that offense.

One of Hoefler’s newsletters dealt with “Layoffs Fairchild style” describing how Fairchild employed three unique tactics for implementing lay-offs. The paging system layoff, the locked door layoff, and the retroactive layoff.  How did those work?

The Paging System Lay-off
This was the standard.  I witnessed this one many, many times.  —— It’s Friday morning. We’re all huddled together in the cafeteria.  Around 9AM the paging system cranks up. “Bob Martin 2867”.   —–   Everybody knew what that meant. Bob Martin (who was a real person and a really delightful guy) knew what it meant too. Bob or some similar victim would stand up and start shaking hands. After he said goodbye to everyone, he’d walk over to the phone and call 2867. 2867 was, of course, the HR department (Called “personnel” in those days). “Bob, this is Bill, can you drop by to see me?” That would be the last that anyone would ever see or hear of Bob Martin.

The Locked Door Layoff
I never saw this one, but Hoefler swore it happened.  I think it may have been used up at the R&D facility  — that’s where the best kept technical secrets resided. There was great fear in those days that company secrets would be stolen by people leaving the company. The Basic Data Handbook was the result of a lot of work that Fairchild rightly didn’t want to fall into the hands of the start-ups who were trying to eat Fairchild’s lunch.  On the other hand, anyone who was leaving for any reason would be tempted to take a copy of it on his way out.   How could you keep that from happening?

According to Hoefler, if you were going to lay off someone in possession of a lot of key knowledge, then the way to do it was to have the facilities department change the lock on the victim’s door the night before. Then, when the victim arrived in the morning and found his key wouldn’t open the door, he’d go see his boss who would then lay him off. That way he had no pre-warning and couldn’t sneak the key information out before the axe fell.

The Retroactive Layoff
This happened if you were unlucky enough to be selected for downsizing when you were out on vacation.  When the victim returned he was informed that he had been laid off and that there was good news and bad news:

“The good news is we gave you two weeks of severance pay.”

“The bad news is you were laid off three weeks ago.”

Perversely enough, I don’t think it was as bad for the victims as it might seem at first blush.  The valley was rife with start-ups and many of them were hiring.  I’d venture to guess that the victims got jobs that were as good or better in short order and that their careers played out better than they might have if they’d stayed at Fairchild.

This story may seem a bit frivolous  —  not to any particular point.  But there is a point.  It’s a snapshot of how Fairchild was back in the day, and to a lesser extent how the entire semiconductor community was.   It was seen by all and consequently shaped the thinking of future generations.  Jerry Sanders,  for example,  watched this unfold and used  it to mold some of the management theories that he would later employ.  (See my week #11 AMD story when it’s published in four weeks).  Jerry,  by the way, once said:

“Being fired by Fairchild was the best thing that ever happened to me.”

Next week.  RTL, DTL, TTL.  What was it?  Who cares?

See the entire John East series HERE.

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2019 GSA Silicon Summit and SiFive

2019 GSA Silicon Summit and SiFive
by Daniel Nenni on 06-28-2019 at 8:00 am
Categories: Events, IP, RISC-V, SiFive
2 Comments

Naveed Sherwani, President and CEO of SiFive, did the keynote for this year’s Silicon Summit. This is one of the premier events for the C level executives in Silicon Valley, absolutely. Naveed is one of the top visionaries for the semiconductor industry and he certainly did not disappoint this time or any other time in my experience.

Naveed started off comparing the semiconductor industry to the software industry. For example, their growth is 10x in 1 year while ours is 10x growth in 10 years. This is very relevant now that AI is driving the semiconductor industry because AI is software centric, right? The SemiWiki bloggers and I have been doing serious amounts of coverage on Artificial Intelligence. AI now drives the largest share of traffic on SemiWiki.com as it touches ALL of the market segments that we closely watch: IoT, Automotive, 5G, and Security.

Naveed did a nice AI overview and I now have the slides so here is a brief summary:

Fast Tracking Silicon and Systems Design for the Edge

The interesting thing here is that AI chips are domain specific so there will be no single provider like Intel used to be for CPUs and Nvidia for GPUs. The result being that systems companies will ultimately rule this domain ( as they now do with SoCs) with custom silicon when the AI market matures, my opinion.

This all started on the edge devices with mobile companies putting AI cores inside SoCs. These Neural Engines were used for facial recognition and other machine learning and inferencing tasks. Cloud companies are also making domain specific AI chips. Google announced Tensor in 2016 at the Google IO Conference. In 2018 Google announced the third generation TPU plus an edge TPU for cloud inferences. Other cloud companies have followed suit making custom silicon for their data centers.

The worldwide public cloud business is expected to grow more than 17% in 2019 to a record $200B+. In 2022 it should exceed $300B so spending a couple of hundred million on making your own chips to differentiate your cloud services is an easy thing to justify, right?

The result is a major semiconductor disruption, not unlike the fabless transformation we experienced in the late 1980s and early 1990s. Systems companies design chips differently than traditional fabless companies. They are not bound by chip margins since they do not sell the chips so budgets are much more flexible. Semiconductor ecosystem companies such as foundries, EDA and commercial IP companies have done quite well as a result. FPGA prototyping companies specifically have done very well since the systems companies have a significant software burden that can be addressed more quickly through prototyping and emulation. AI models are also fast moving so you definitely want to prototype.

Speaking to that, one of the slides Naveed used repeated the notion that 7nm chip development is too costly at more than $500M. This number has been floating around the ecosystem for some time and I have found it to be patently FALSE. Even if you include embedded software development it is not even close to $500M. eSilicon has already taped out some very large chips at 7nm for a fraction of that price. I have discussed 7nm design costs with some of the top fabless semiconductor companies in California and every single one of them laughed or smirked at the $500M 7nm chip price. And now I’m reading that 5nm chips will cost $600M?

SEMICON West is coming up so I will continue my inquiry into this FUD but you have to ask yourself “self, who is it exactly that benefits from this kind of 7nm smear campaign?” The answer of course is the analysts who are trying to sell their reports. Unfortunately, they are cutting off our noses to spite our faces since investment in fabless companies is at risk with such inflated propaganda, but I digress…

Naveed also mentions China which is appropriate since you cannot have a semiconductor discussion these days without talking about China. Naveed points out that China is leading the world AI funding with 48% compared to the US at 38% and this will continue in my opinion. Even so, I would say that in total, US funding will result in many more production chips than China since China is still relatively new at the fabless business while the US has 30+ years of experience.

According to Naveed the big difference between software and semiconductor design is development costs (true), development cycle (true), and too many experts needed (very true).

Naveed then transitioned into the SiFive value proposition for emerging AI chips. Remember, SiFive acquired ASIC provider Open-Silicon last year. The result is a cloud based do-it-yourself ASIC service featuring RISC-V 32 and 64 bit CPU cores and supporting IP in what Naveed calls “templates”.

SILICON AT THE SPEED OF SOFTWARE

Design RISC‑V CPUs in an hour. Get custom SoCs in weeks, not months. Impossible? Not anymore. Discover a fundamentally new approach to creating custom SoCs.

START DESIGNING

Bottom line: SiFive is all about removing the barriers to getting emerging fabless chip companies and new-to-chip-design systems companies into silicon. Design starts and finishes are the lifeblood of the semiconductor industry so I say BRAVO!

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Double-digit semiconductor decline in 2019

Double-digit semiconductor decline in 2019
by Bill Jewell on 06-27-2019 at 4:00 pm
Categories: Semiconductor Intelligence, Semiconductor Services

The global semiconductor market is headed for a double-digit decline for the year 2019 after a decline of 15.6% in first quarter 2019 from fourth quarter 2018. According to WSTS (World Semiconductor Trade Statistics) data, this was the largest quarter-to-quarter decline since a 16.3% decline in first quarter 2009, ten years ago. Most recent semiconductor market forecasts reflect this trend. 2019 forecasts range from -7.2% from IDC to -15.0%, our latest Semiconductor Intelligence forecasts. Other forecasts are in the range of -11% to -13%.

Available forecasts for 2020 show a return to growth, ranging from +5.4% from WSTS to +8.7% from Mike Cowan. Our Semiconductor Intelligence forecast for 2020 is +8.0%.

The reported first quarter 2019 revenues of the major semiconductor companies confirm the severity of the decline from fourth quarter 2018. The three largest memory companies all reported declines of over 20%. Samsung revenues were down 23% and SK Hynix revenues were down 32%. Micron’s quarter ended February 28 showed a 26% revenue decline from the prior quarter while its quarter ended May 31 showed an 18% decline. Micron sees early signs of a recovery in the memory market in the second half of calendar 2019. Its revenue guidance for the current quarter ending August 31 ranges from a 2% decline to a 10% decline, with a midpoint of a 6% decline. Samsung also sees demand stabilization from some memory applications.

Most non-memory semiconductor companies also saw major revenue falloff in first quarter 2019, ranging from STMicroelectonics’ -22% to Texas Instruments’ -3.3%. Qualcomm, Nvidia and Infineon showed low single digit revenue increases. The outlook for second quarter revenues of non-memory companies is mainly positive. MediaTek expects 17% growth from first quarter based on growth in smartphones in the seasonally strong second quarter. Nvidia guided to a 15% increase due to growth in gaming and artificial intelligence (AI) applications. Texas Instruments, STMicroelectronics and Infineon expect low single-digit quarter-to-quarter growth in second quarter, but the low end of guidance for each is a decline. Of the non-memory companies, only Intel expects a decline (-2.9%) based on channel inventory adjustments and concern over the U.S.-China trade issues.

The current weakness in the semiconductor market is due to a supply/demand imbalance in the memory market, weak key end equipment markets and global economic concerns. IDC forecast a 1.9% decline in smartphone unit shipments in 2019, following a 3.4% decline in 2018. IDC expects smartphones to recover to 2.8% growth in 2020. Gartner projected total PC plus tablet units will decline 0.7% in 2019, a slight improvement from a 2.5% decline in 2018. Gartner does not see a shipment recovery in 2020, with a decline of 0.8%.

Annual Change 2018 2019 2020 Source
Smartphones -3.4% -1.9% 2.8% IDC, May 2019
PCs & tablets -2.5% -0.7% -0.8% Gartner, April 2019
Global GDP 3.6% 3.3% 3.6% IMF, April 2019

The International Monetary Fund (IMF) sees global GDP growth decelerating from 3.6% in 2018 to 3.3% in 2019, bouncing back to 3.6% in 2020. The IMF cited the U.S.-China trade dispute, slowing consumer demand in Europe, and Brexit uncertainty in the UK as factors leading to the GDP deceleration in 2019.

The good news is the semiconductor market appears headed for recovery by the second half of 2019. The current slowdown is primarily due to memory and some inventory issues. End equipment markets are weak but should improve in 2020. GDP growth is slowing in 2019, but most economic forecasters do believe a recession is likely and growth should return to 2018 levels in 2020. Although a significant semiconductor market decline is inevitable in 2019, we at Semiconductor Intelligence feel confident with our 8% growth forecast for 2020.

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SPIE Advanced Lithography Conference – Imec design papers

SPIE Advanced Lithography Conference – Imec design papers
by Scotten Jones on 06-27-2019 at 10:00 am
Categories: Events, Lithography, Semiconductor Services, TechInsights

At the SPIE Advanced Lithography Conference Imec presented several design papers and I have had the opportunity to review the papers and speak with the authors. In this summary I am going to address three emerging areas in order of when I think they may be implemented from soonest to latest.

Specifically, I will discuss:

  1. Buried Power Rail (BPR)
  2. Backside Power Distribution
  3. Complementary FET (CFET)

Buried Power Rail

Logic designs are made up of standard cells. The size of a standard cell depends on metal pitch, cell track height, poly pitch and whether it is single or double diffusion break. For many years scaling was driven by metal pitch (MP) and poly pitch (PP) scaling, but MP scaling faces lithographic and resistance challenges and PP scaling has slowed due to device issues. The use of Design Technology Co-Optimization has led to track height scaling becoming a major scaling knob, but track height scaling also presents challenges.

Figure 1 shows scaling with a 40% per node area shrink goal.

Figure 1. Area scaling.

Scaling limitations also result in more restrictive design rules.

Figure 2 illustrates the evolution of designs by node.

Figure 2. Design evolution with node.

 From figure 2 it can be seen that as we have moved to smaller nodes 2D poly and metal layouts have given way to 1D layouts and more complex Middle Of Line (MOL) interconnect schemes.

Figure 3 presents the number of fins versus track height. The height of a cell is the MP multiplied by the number of tracks. As the MP and number of tracks are reduced there is less room for fins and fin depopulation is required.

Figure 3. Scaling challenges.

 As cell heights have scaled from 9, to 7.5, to 6.5 and eventually 5 tracks the number of fins per cell has been reduced from 4 to 3 to 2 and eventually 1 fin. This will also result in decreased drive current unless something is done to otherwise optimize the device.

Power rails for cells (Vdd and Vss) are typically some multiple of MP (see upper left in figure 3). At 5 tracks the spacing is so tight that in order to realize the cell the power rails must be moved out of the MOL interconnect layers and down into the substrate as Buried Power Rails (BPR). An illustration of BPR is presented in the CFET section.

BPR present fabrication and material challenges with the BPR having to survive subsequent high temperature transistor fabrication steps. The material used for the BPR has to be selected for low resistance and high thermal stability. One target material is Ruthenium but Ruthenium is very expensive.

 Backside Power Delivery

While BPR helps with the layout challenges to get to a 5-track cell, there are still issues with IR-drop due to the rising resistance of the very thin interconnect lines. Backside power delivery addresses these issues by creating large power distribution lines on the underside of the device and connecting them up to BPR using Micro Through Silicon Vias (µTSV).

Figure 4 illustrates the backside power delivery process flow.

 Figure 4. Backside Power Delivery process flow.

 The backside power delivery process flow begins with a wafer that has buried power rails.

  1. The wafer is temporarily bonded to a carrier wafer.
  2. Wafer thinning is performed.
  3. The backside passivation is patterned.
  4. High aspect ratio through silicon vias (TSV) are formed and filled.
  5. Backside power rails are formed.

The process requires extreme wafer thinning and precise location fo very small TSVs.

 Complementary FET (CFET)

The CFET concept is simple, instead of fabricating nFET and pFET devices next to each other they are stacked, see figure 5.

Figure 5. CFET scaling concept.

 As was discussed in the section on buried power rails as track height is scaled down fin depopulation occurs with a single fin expected for a 5 track cell.

The CFET design break the p to n separation distance bottle neck and can enable a 4 track cell height with 2 fins, see figure 6.

Figure 6. CFET scaling.

 Vertically stacking nFET and pFET devices creates and interconnect challenge and requires more complex middle of line (MOL) approaches. Figure 7 illustrates a 4 track cell in cross section and figure 8 illustrates a 3 track cell in cross section.

Figure 7. Cross section of 4 track CFET cell.

Figure 8. Cross section of 3 track CFET cell.

Finally, figure 9 summarizes the advantages of the CFET concept.

Figure 9. Benefits of a CFET.

 Conclusion

The challenges of continued logic scaling are being met with innovative new process designs. Buried power rails and backside power distribution address power distribution requirements for low resistance in small areas.

CFETs present an opportunity to address horizontal scaling limits with a 3D logic approach.

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Integrated SIMs Will Unlock IoT Growth

Integrated SIMs Will Unlock IoT Growth
by Bernard Murphy on 06-27-2019 at 5:00 am
Categories: 5G, IoT, IP, Security, Synopsys
2 Comments

I’m a believer that connectivity for the IoT at scale (the trillions of devices that the industry predicts) has to be cellular. This is partly based on reach, particularly outside urban areas, but is mostly based on the financial implications of that scale. Yes, you can build infrastructure for say local Wi-Fi support with backhaul to cellular or wired internet, but that comes with capital and on-going operational costs, together with varying levels of quality and security which each organization has to bear. In an age of virtualized everything, this makes no sense. We let the people who specialize in building and running hyperscale datacenters offer us cloud computing. We should let the people who specialize in offering global, interoperable mobile communications (MNOs) provide our IoT communications infrastructure.

Example ISIM implementation

This comes with the added benefit that MNOs are motivated to ensure that anyone who connects is authorized to do so, through the authentication services provided by the SIM cards we know so well. SIM cards would be wildly impractical for the IoT – too easy to hack and too painful to maintain across massive networks of edge devices. This has driven development of embedded SIMs (eSIMs), over-the-air (OTA) programmable SIM devices now available in consumer products such as the iPhone XR and XS.

But eSIMs are still separate chips, adding bill of materials cost and power consumption to your product, neither desirable in IoT devices which are generally expected to be very cost-sensitive and depending on very infrequent maintenance to change batteries. The natural next step should be to integrate the eSIM functionality into your SoC, right?

That turned out to be not so easy. I talked to Michael Moorfield, head of Product at Truphone and Ruud Derwig, Sr staff engineer at Synopsys about this. Truphone is an interesting company providing (among other things) an MVNO service (mobile virtual network operator) particularly for international businesses and IoT solution providers needing seamless mobile connectivity around the world. So they know a thing or two about cellular, MNO services and particularly eSIMs. They already provide a full software stack ecosystem for eSIM for the IoT. Now they’ve been working with Synopsys to move this to the next step – integrated SIM (iSIM).

So what’s the big deal in translating an eSIM into an IP? According to Ruud, that’s where this gets tricky. SIMs are held to a very high security standard, much higher than the sadly still common “we should really do something about security in this product” IoT expectation. MNOs don’t want anyone stealing access, from them or from a legitimate customer, since that access is billable; stealing access here connects very directly to stealing money. So SIM security design is very similar to the security you find in chipped credit cards. It needs to be shown to be as near unhackable as we know how to build today (there is no industry standard yet for this, but it wouldn’t be surprising to see one emerge). This means unhackable not just against logical/software attacks, but also against semi-invasive attacks (timing, DPA and RF side-channels) as well as more invasive attacks through power or clock glitching.

The hardware subsystem has been crafted by Synopsys and Truphone around existing DesignWare components: the ARC SEM processor, crypto accelerators, a secure external memory controller, a true random number generator and other features, all providing multiple mechanisms for protection and tamper detection. Notable in the software stack sitting on top of this hardware is the Java Card platform, the same system used in credit card chips.

Add to this that Truphone is already GSMA-accredited for generating and processing sensitive SIM and MNO data and I have to believe whatever iSIM standards will be, they’ll look pretty much like this solution. You can learn more about this joint development HERE.

 

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Dynamic Spectrum Allocation to Help Crowded IoT Airwaves

Dynamic Spectrum Allocation to Help Crowded IoT Airwaves
by Tom Simon on 06-26-2019 at 10:00 am
Categories: 5G, EDA, IoT, Magillem, Mobile

Radio frequency bandwidth has become a precious commodity, with communications companies paying top dollar for prized pieces of the spectrum. However, many radio bands are not often used efficiently. Many existing radio protocols exchange data on a fixed pair of frequencies, tying up those frequencies for other users. When this happens other users of those frequencies experience congestion that affects QoS. Then on the other hand there are often times in a reserved band where no licensed user is communicating at all. Years ago, it was recognized that if devices could more intelligently use the existing frequencies, efficiency could be dramatically improved.

The proliferation of wireless IoT devices is increasing crowding and the demand for improved efficiency. Additionally, it is no longer feasible to build a unique radio in a device to support each RF standard the devices requires. The solution to these problems is coming from software defined radio (SDR) combined with the intelligence to allow switching bands dynamically to utilize available areas of the spectrum. This new method of operation is called Cognitive Radio.

Cognitive Radio will encourage smart usage of IoT spectrum

Cognitive Radio, which allows dynamic switching between bands to access underutilized spectrum, has recently been made feasible through advances in radio design. The challenge has been to build radios that can work on a wide range of frequencies. Moving as much of the RF processing to the digital domain is a major component of this solution. This is coupled with the adoption of Sigma Delta Analog to Digital Converters (SD-ADC) for the down-conversion.

When properly implemented SD-ADCs can reduce quantization noise though oversampling and noise shaping, dramatically improving the signal to noise ratio.  Designers face many choices in the implementation the RF stage. Also, there is significant interplay between the digital portion and the RF stage, especially in tuning the baseband filters. Each wireless standard, such as GSM, LTE, 802.11, etc., has different signal requirements that must be accommodated in the radio.

Modeling and simulating the radio design is extremely important to ensure that it will operate properly once it is implemented and fabricated. SystemC and SystemC-AMS are proving to be useful tools in understanding the performance and behavior of radio designs. Choices need be made about design partitioning, parameter selection, software design, etc.

I recently had a chance to talk to Jean-Michel Fernandez, Embedded Systems Product Line Director, from Magillem about how IP-XACT can help this early design process. With SystemC models for each element in the design, it is easy with their MVP product to create a virtual prototype and then run simulation. This gives designers the ability to experiment with architecture, for instance relocating discrete RF components onto the SOC die. Also, the integration of software and hardware can be verified early in the design process. Later in the flow if the block level RTL has been brought into IP-XACT, the system RTL can be generated for synthesis, targeting an FPGA or ASIC.

With Magillem’s IP-XACT based MVP solution it is easy to assemble the receiver chain and then configure each component. Test benches can also be managed with MVP, so that everything needed for system level simulation is easily available. It is also straightforward to import legacy IP. MVP can automatically package existing SystemC code into IP-XACT.

Cognitive radio is one small piece in the increasing intelligence of electronic systems. It should significantly improve the overall efficiency and utilization of the airwaves. This will be seen by consumers in the form of lower communications costs, as well as in higher reliability and throughput. Magillem has information about their MVP product for managing design configurations and creating virtual prototypes on their webpage.

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Micron beats subdued guidance on output cuts

Micron beats subdued guidance on output cuts
by Robert Maire on 06-26-2019 at 5:00 am
Categories: Semiconductor Advisors, Semiconductor Services
2 Comments

2020 capex likely down at least 20% vs 2019 DRAM & NAND price drops versus slowing capacity. Investors happy cause it could have been worse.

Micron reported $1.05 in Non-GAAP EPS beating street consensus of $0.79 by $0.26. While this looks like a big beat, we would remind investors that estimates for the quarter were about $1.35 just four short months ago before further previous downward guidance. Revenues came in at $4.79B versus reduced street expectations of $4.7B.

Guidance is for revenues of $4.5B +-$200M and EPS versus street of $4.56B and EPS of $0.45+-$0.07 versus street of $0.70.  Guidance is obviously low but likely “sandbagged” just like the reported quarter.

Still cutting wafer starts to reduce supply to prop up pricing
Micron continues to cut wafer starts another 5% to try to reduce the oversupply condition which was worsened by Huawei.  The company made it clear that the market remains “oversupplied” even though the oversupply may be lessening.

We would imagine that Micron and other memory makers will continue to cut output until we getting into a better supply/demand balance and pricing starts to recover.

This supply/demand cyclicality is typical of many commodity like markets such as oil and other global markets and it sound come as no surprise to seasoned investors that the down part of the cycle always takes a significant amount of time to work off the excess capacity.

It should also be abundantly clear that when you are cutting capacity your capital spending to increase capacity goes to near zero levels.  Spending on “technology buys” continues, but raw capacity they don’t need right now.

2020 capex to be “meaningfully down” versus 2019
Micron has already cut 2019 capex from the prior $10.5B to the current expected $9.0B with a current run rate of about $8B.  While Micron did not specifically quote 2020 capex plans as they are still in flux, they did say “meaningfully down” from 2019’s $9B.  We think “meaningfully ” is code for 20% or more, not just 10%. That would suggest getting down to a “7” handle or lower. That would be down well over 30% from the peak but not as far down as Samsung which drove its capex off a cliff.

Makes it really hard for 2020 to be an “up” year for semicap
With Micron clearly cutting 2020 versus 2019 and Samsung in the exact same boat, we can’t imagine any memory maker who will be planning on a capex increase in 2020 which would imply we are not going to see a recovery that some optimists are suggesting.

Months ago we said that the current downcycle would be longer and deeper than previously expected due to China and only in the last couple of weeks have most analysts finally figured that out.  Many are still in denial by suggesting that 2020 will be up significantly.  Its not like logic and foundry are going to double spending to offset the ongoing memory weakness…its just not going to happen……so get over it.

Bit growth continues without capex increasing
What most investors and many junior analysts don’t get is that memory bit growth can continue without an increase in capex and can in fact see strong bit growth in a declining capex environment.  By continuing to follow Moore’s law, we get more bits in less silicon without increasing capex proportionately.

We have long held to the view that there are in fact two cycles underlying the industry. The technology spending cycle and the capacity spending cycle.  Technology spending (to further Moore’s law) usually goes on almost no matter what while capacity spend can go to near zero when the industry is over supplied such as it is now.

Right now Micron and Samsung can easily keep up with bit growth just with technology improvements to the next node.

Technology spend causes semicap share shift
When capex is focused on technology rather than capacity, more money tends to be spent on yield management and lithography which are the two primary drivers of Moore’s law.  This suggests that spending related to KLAC and other metrology/inspection companies as well as litho spending, with ASML, tends to hold up better than basic process tool sales

The Stocks- the “it coulda been worse” rally
Micron’s stock was up 8% in the aftermarket due to the fact that it wasn’t as bad as it could have otherwise been even though it was worse than expected 4 months ago.  Investors don’t seem to have quite latched on to the great miss on forward guidance. Basically anything is better than a miss.

We would not be surprised if semicap names are up in a sort of “kneejerk” reaction that will be positive across the chip market even though the news for semicap names is very negative given the capex guidance for 2020 being down which blows a hole in the “capex recovery in 2020” theory. But short sighted investors and analysts will likely latch on to the hope of the beat forgetting how reduced the expectations were.

We think the reduced 2020 capex comments clearly reflect the severity of the oversupply situation and Micron is voting with its feet in saying that things won’t get better enough in 2020 to warrant a capex increase.  We agree.  We think memory pricing will continue to stabilize as output continues to be cut but we see no huge rebound in demand that would force memory makers to increase capex any time soon.

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Upcoming HBM and CDM ESD Verification Seminar in Taiwan

Upcoming HBM and CDM ESD Verification Seminar in Taiwan
by Tom Simon on 06-25-2019 at 10:00 am
Categories: EDA, Events, Magwel

The electrostatic discharge that occurs in lightening, as seen in the picture below, can cause serious damage to the objects on the ground. Over centuries mankind has devised ways, such as lighting rods and arresters, to deflect the energy so it is dissipated harmlessly. The same drama plays out on modern semiconductors due to electrostatic build up on people, equipment or the devices themselves. MOS semiconductor devices can easy be damaged or destroyed by the currents and voltages that occur in discharge events during fabrication, assembly or handling.

The very first MOS devices could be destroyed simply by handling them with bare hands. Over the years, on-chip ESD protection has improved dramatically. However, nearly every semiconductor device needs to contain ESD protection circuitry. Properly designed protection networks are transparent during normal operation but are triggered when the device is exposed to an ESD discharge event. Designing these protections is a complex task and verifying them can also be a challenge. While most circuit designers leave the job of designing and verifying the ESD protections to ESD experts, it behooves all designers to understand the design considerations and trade-offs in ESD protection methods.

In Taiwan on July 16th interested engineers and managers will be able attend a seminar organized by Prof. Ming-Dou Ker, where Magwel Chairman and CEO Dundar Dumlugol will discuss the challenges of chip level ESD verification. The presentation will outline each of the steps involved in taking the layout of a chip and modeling it for CDM and HBM simulation. These steps include detailed resistance extraction of the involved nets. Then for HBM and CDM, either TLP or vf-TLP models are used for the ESD devices. Because of snap-back behavior in ESD devices, SPICE simulation is not an option. Dr Dumlugol will discuss the optimal static and dynamic simulation methods for both HBM and CDM.

In addition to triggering intended ESD devices, ESD events can cause triggering of parasitic sneak paths, and parasitic Bipolars. Failure modes can include electromigration and voltage overstress. ESD events can also cross between power domains.  ESD protection failures can affect IO devices and devices in the chip’s core. Dr. Dumlugol will discuss these various failure modes and ways that they can be detected before tapeout.

The Seminar is titled “Simulation Based Chip-Level Verification Methodology Of HBM and CDM Events” and will be held July 16th at Hsinchu Jiaotong University in Taiwan from 1:30 PM to 4:30 PM. At the end there will be a question and answer period. Seating is limited and advance registration is available online at http://www.alab.ee.nctu.edu.tw/~esd/reg.html

The seminar will include a demonstration using the techniques discussed in the presentation. This seminar is unique opportunity for learning about the risks and the underlying mechanisms of ESD failures, as well as practical techniques to prevent them in finished silicon. Here is a link to the PDF invitation download.

 

About Magwel

Magwel® offers 3D field solver and simulation based analysis and design solutions for digital, analog/mixed-signal, power management, automotive, and RF semiconductors. Magwel® software products address power device design with Rdson extraction and electro-migration analysis, ESD protection network simulation/analysis, latch-up analysis and power distribution network integrity with EMIR and thermal analysis. Leading semiconductor vendors use Magwel’s tools to improve productivity, avoid redesign, respins and field failures. Magwel is privately held and is headquartered in Leuven, Belgium. Further information on Magwel can be found at www.magwel.com

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Eta Compute Showcases Continuously Tuned DVFS

Eta Compute Showcases Continuously Tuned DVFS
by Bernard Murphy on 06-25-2019 at 6:00 am
Categories: AI, Eta Compute, IoT, IP

If you practice in advanced levels of power management, you know about dynamic voltage and frequency scaling (DVFS). This is where you allow some part of a circuit, say a CPU, to run at different voltages and frequencies depending on acceptable performance versus thermal tradeoffs and battery life on a mobile device. Need to run fast? Crank up the voltage and frequency to run a task quickly, then drop both back down to save power and allow generated heat to dissipate.

Intelligent compute at ultra-low power

DVFS is a well-known technique in PCs and servers, where boosting performance (for the whole processor) is an option and slowing down to cool off is the noticeable price you have to pay for that temporary advantage. This method is used at a more fine-grained level in the application processor at the heart of your smart-phone, where multiple functions may host their own separate DVFS domains, switching up and down as your usage varies. This method to balance performance versus power-saving can be especially important in any edge application demanding long battery life.

DVFS as commonly used is not an arbitrarily tunable option. System architects specify a fixed set of voltage/frequency possibilities, commonly two or three, then these options are hardwired into the chip design. In synchronous circuit design each clock option comes at a cost in complexity and size for the PLL, dividers or however else you generate accurate clocks.

But what if you’re using self-timed logic? Not necessarily for the whole SoC, but certainly for some critical components. I know of only one independent set of IP options today, from Eta Compute, so I’ll describe my understanding of how they implement tunable DVFS to get ultra-low power in intelligent IoT devices, down to a level that harvested power may be an usable complement to a backup battery. This is based on my discussion with Dave Baker, Chief architect at the company.

I introduced this company a while ago, on their introduction of a self-timed Cortex M3 core which would be a natural to use in this kind of IoT device. Since then, they have also struck a partnership with NXP to offer a CoolFlux DSP which hosts AI computation. As a reference design based on these cores they have developed their ECM3531 testchip with all the usual system functions, serial interfaces, a variety of on-board memory features and a 2-channel ADC interface (to connect to sensors). The system is supported by the Apache MyNewt OS, designed for the IoT, with built-in support for BLE, Bluetooth mesh and other wireless interfaces. Eval boards are already available.

OK, so far pretty standard except for the self-timed cores, but here comes the really clever part. Because this is self-timed logic, performance can be tuned simply by adjusting the voltage supply to the core. If the converter supplying that voltage is tunable, you can dial-in a voltage and therefore a performance. Eta Compute provide their own frequency-mode buck converter for this purpose. And you can tune the converter through firmware. The company’s RTOS scheduler monitors idle-time per heartbeat and computes if idle time is dropping, it should raise the voltage, whereas if idle time is growing, it can afford to lower the voltage. An optimal setting can be tuned to fall somewhere between a target setting for an application stage down to a frequency below which interrupt latencies may become a problem.

Now compare this approach with what I call run-fast-then-stop and Dave calls race-to-idle. When you have work to do, you crank the frequency (and voltage) to the maximum option, do the work as fast as you can, then drop back to the lowest frequency/voltage option. There is timer uncertainty in switching so power wasted during those transitions, scaling with the size of the transition. And of course power (CV2f) during the on phase is high. Compare this with the Eta Compute approach. On-voltage scales up only as high as will meet the idle-time objective, typically much lower than the peak voltage in the first approach. And power wasted during switching is correspondingly lower because transition times are shorter. Even the idle voltage can be lower since this too is tunable, unlike the hardwired option in conventional DVFS.

Eta Compute have run CoreMark and ULPMark benchmarks against a number of comparable solutions and are showing easily an order of magnitude better energy efficiency (down to 5mW at 96MHz), along with IoT and sensor application operating efficiency at better than 4.5uA/MHz. So yeah, you really can run this stuff off harvested power. In fact, they have shown a solar-powered Bluetooth application running battery-less at 50uW in continuous operation.

I skipped a lot of detail in this description in the interest of a quick read. Dave told me for example that the interconnect is also self-timed, important because buffers in the interconnect consume a lot of power. Therefore intelligent scaling of voltage in the interconnect is equally important. If you want to dig more into the details, click HERE.

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Lithography For Advanced Packaging Equipment

Lithography For Advanced Packaging Equipment
by Robert Castellano on 06-24-2019 at 10:00 am
Categories: Information Network, Semiconductor Services

Advanced IC packaging, such as fan-out WLP (Wafer Level Packaging) and 2.5D TSV (Through Silicon Via) will drive the packaging equipment market, particularly lithography. This will help specific equipment manufacturers in 2019, since the WFE (Wafer Front End) market will drop 17%. But the Back-End lithography market, led by Veeco.

Advanced Packages

The IC industry is evolving as new technologies replace old ones. As dimensions on advanced ICs move below 10nm, packages that house and protect them from the environment and aid in bonding to the printed circuit board are also evolving. Traditional wire bonding is being replaced by flip chip (FC) bonding, which, in turn, is being replaced by wafer level packaging (WLP).

Sales in Advanced Packaging are driven by shipments of lithography systems and upgrades to Outsourced Semiconductor Assembly & Test companies (or OSATs) and foundry customers in support of advanced packaging processes, such as Fan-Out Wafer Level Packaging (FOWLP) and Copper Pillar. OSAT growth and capacity will be driven by broader technology trends such as artificial intelligence (AI), mobile, autonomous vehicles, big data and 5G deployments.

 

Lithography Market

Competition in the advanced packaging lithography market comes from various reduction steppers and proximity and projection aligner companies such as: Canon (CAJ), EV Group, Rudolph Technologies (RTEC), Shanghai Micro Electronics Equipment Co., SUSS MicroTec, Veeco, and USHIO.

Chart 2 shows market shares for the advanced packaging lithography market for 2018, according to our report. The top three companies – Canon, Veeco, and EV Group held a 70% share of the market, and if we include SUSS, these companies held an 85% share of the market.

Chart 3 shows the 2018/2017 YoY growth of the advanced packaging lithography companies. Veeco grew 35% after a rocky transition following the acquisition of Ultratech. Veeco’s lithography tool is broadband stepper, which supports all three wavelengths–436nm, 405nm and 365nm. These are produced by a broadband spectrum mercury light.

Canon, a strong contender in the WFE and FPD (Flat Panel Display) lithography markets, grew 20.5% YoY. The company is utilizing expertise from a strong installed base of thousands of lithography tools, combined with improved optic resolution, to make reduction steppers a viable technology in advanced packaging.

According to The Information Network’s report entitled “Flip Chip/WLP Manufacturing and Market Analysis,” the number of ICs packaged in WLP will exhibit a CAGR of 6.8%. In contrast, IC growth in 2019 is forecast to drop 12.1% by industry consortium WSTS. Chart 1 illustrates the growth of WLP in terms of number of devices.