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Lithography For Advanced Packaging Equipment

Lithography For Advanced Packaging Equipment
by Robert Castellano on 06-24-2019 at 10:00 am
Categories: Information Network, Semiconductor Services

Advanced IC packaging, such as fan-out WLP (Wafer Level Packaging) and 2.5D TSV (Through Silicon Via) will drive the packaging equipment market, particularly lithography. This will help specific equipment manufacturers in 2019, since the WFE (Wafer Front End) market will drop 17%. But the Back-End lithography market, led by Veeco.

Advanced Packages

The IC industry is evolving as new technologies replace old ones. As dimensions on advanced ICs move below 10nm, packages that house and protect them from the environment and aid in bonding to the printed circuit board are also evolving. Traditional wire bonding is being replaced by flip chip (FC) bonding, which, in turn, is being replaced by wafer level packaging (WLP).

Sales in Advanced Packaging are driven by shipments of lithography systems and upgrades to Outsourced Semiconductor Assembly & Test companies (or OSATs) and foundry customers in support of advanced packaging processes, such as Fan-Out Wafer Level Packaging (FOWLP) and Copper Pillar. OSAT growth and capacity will be driven by broader technology trends such as artificial intelligence (AI), mobile, autonomous vehicles, big data and 5G deployments.

 

Lithography Market

Competition in the advanced packaging lithography market comes from various reduction steppers and proximity and projection aligner companies such as: Canon (CAJ), EV Group, Rudolph Technologies (RTEC), Shanghai Micro Electronics Equipment Co., SUSS MicroTec, Veeco, and USHIO.

Chart 2 shows market shares for the advanced packaging lithography market for 2018, according to our report. The top three companies – Canon, Veeco, and EV Group held a 70% share of the market, and if we include SUSS, these companies held an 85% share of the market.

Chart 3 shows the 2018/2017 YoY growth of the advanced packaging lithography companies. Veeco grew 35% after a rocky transition following the acquisition of Ultratech. Veeco’s lithography tool is broadband stepper, which supports all three wavelengths–436nm, 405nm and 365nm. These are produced by a broadband spectrum mercury light.

Canon, a strong contender in the WFE and FPD (Flat Panel Display) lithography markets, grew 20.5% YoY. The company is utilizing expertise from a strong installed base of thousands of lithography tools, combined with improved optic resolution, to make reduction steppers a viable technology in advanced packaging.

According to The Information Network’s report entitled “Flip Chip/WLP Manufacturing and Market Analysis,” the number of ICs packaged in WLP will exhibit a CAGR of 6.8%. In contrast, IC growth in 2019 is forecast to drop 12.1% by industry consortium WSTS. Chart 1 illustrates the growth of WLP in terms of number of devices.

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1971 is the year that Intel changed the world

1971 is the year that Intel changed the world
by John East on 06-24-2019 at 5:00 am
Categories: Intel Foundry, John East
5 Comments

The “20 Questions with John East” series continues

From time to time I present the History of Silicon Valley as I saw it to various audiences.  I always enjoy doing that.  I’ve learned that the part that audiences like the most is the Apple / Steve Jobs story.  That’s not hard to understand.  Steve Jobs was truly fascinating! The story that captivates me, though, is this one.  I was working at Fairchild in 1971 watching this story unfold.  It took me 20 years to understand how important it was.  Looking back at it, it still amazes me!!

The years following the Intel 1101 introduction were dramatic!!  In 1970 Intel introduced the 1103 — the world’s first DRAM.  The yields were very poor. They couldn’t ship many. But the concept was born.  The stage was set for the future.  Then came 1971.

In 1971 the 1103 yields improved and they were able to ship large quantities. (In fact, by the time 1973 had ended, the 1103 was the biggest selling chip in the world.)    Also, in 1971, Intel announced the first erasable floating gate memory — the 1702.  The 1702 was a 2K PROM (Programmable read only memory) which stored its contents on the gates of “floating gate” transistors.  This by itself wasn’t particularly exciting,  but there was a twist:  By radiating the die with UV light (Made possible by a see-through lid on the top side of the package),  you were able to erase the contents and then reprogram it.  It wasn’t a PROM after all.  It was the world’s first EPROM (Erasable programmable read only memory).  Finally, in 1971 Intel introduced the microprocessor.  Their first microprocessor, the 4004, was only a 4 bit processor but again, it set the stage.  And oh –  by the way. They went public in 1971 making many of them multi-millionaires.  You couldn’t be more deserving!!

So,  in 1971 Intel commercialized the first DRAM,  introduced the first floating gate memory,  and introduced the first microprocessor.  How impressive is that?  Today – nearly 50 years later –  those three categories comprise well more than half of the world semiconductor market.  (How much more?  Good question.  To come up with a valid number you’d have to know how much embedded memory and how many embedded processors are inside of all the ASSPs that are being shipped.  That’s way above my pay grade  — but I’ll bet Daniel Nenni could do it)

Boy.  Did that ever aggravate us at Fairchild.  We felt like we were working hard, but they were killing us! How in the world did they do it?  How did they invent their way into stardom while at Fairchild we were spinning our wheels?  I’ve met Gordon Moore only twice  —  the first time was at a party at Larry Sonsini’s home (Wilson-Sonsini is the dominant Silicon Valley law firm).  Some time later I sat next to him at some sort of industry dinner back in the early eighties.  I can’t remember what the dinner was for or why I sat next to him, but I do remember the conversation.  I asked him that question:  How did you do it? How did you build and incentivize a team to foster such innovation?  His answer was:  First  – you hire really smart people.  Second – you make it clear that they will get the credit for their work.  And third – you let them know what you wish they would invent.  If you don’t do that, he said, lots of crazy things are going to get invented that you will have no use for.

I don’t think that Gordon could pick me out of a police lineup if he saw me today.  (I hope he never has the opportunity!!) We met only those two times. But, I’ve heard so much about him from some of my friends who worked for him I feel like I know him. Gordon was always known for being modest and unassuming.  He famously drove an old car to work every day so people wouldn’t think he was putting on airs.  He wanted to be seen as a “regular guy”.  Regular guy?  For a guy with an IQ of 200 and several billion dollars in the bank??? Tough to pull off, I suspect. (I wish I had first-hand knowledge.)  But  — if you sit next to him at dinner,  that’s the feeling you get. By the way, Gordon is at least $5B lighter in the wallet than he used to be.  He once donated 175 million shares of Intel to charity.

The Intel story isn’t all glory.  Real life stories never are.  Their worst stretch came in the early to mid-eighties.  Japan Inc had embarked on a plan to conquer the world’s integrated circuit business by taking control of the three M’s:  Memories,  Microprocessors,  and Master slices (gate arrays).  They (the Japanese) were already good at manufacturing.  They already had low costs.  Their strategy was to bomb prices until the American companies, who were less well capitalized and had huge pressure from shareholders to keep earnings high, gave up and got out of the business.  The easiest and most obvious target was the DRAM market.  DRAM prices were dropping like a rock.  Intel began losing money for the first time since their IPO in 1971.  DRAMs, which once represented 90% + of Intel’s revenues, were down to a few percent by 1984.  Even though Intel had invented the DRAM, by 1984 they had no particular strategic or technical advantage.  They were good at DRAMs.  So was everybody else. On the other hand, because of their design win in the IBM PC, they had attained a near dominant position in the microprocessor market.  That market had barriers to entry much higher than DRAMs ever had or could have.  Should they exit the DRAM business?  There were great debates.  A quote from someone inside the company went, “Intel leaving the DRAM business would be like Ford leaving the auto business”.  In the end they opted to exit.  The P&L was messy for a couple of years.  A quote from their 1986 Annual Report went,   “We’re pleased to report that 1986 is over.” Then, their shares grew steadily until their market cap hit nearly $300 billion.  I guess it was the right decision.

When I was young, America was better at everything.     Cars, steel, shoes, clothing, engineering, etc.  Everything!!  “Made in Japan” was a derogatory term.  China didn’t matter at all in the world economy.  Taiwan and Korea were trying to matter, but they didn’t.  Today, as a nation, the USA has lost a lot of that.  Industries that used to pay for our way of life are now struggling in America.  But  — we’re still really strong in high tech.  Sure, we have competition, but we’re the force to be reckoned with.  If there were a king of high tech, it would be us.  Without the contributions of Intel (And Microsoft) that wouldn’t be true.

Thanks Gordon.  Thanks Bill Gates.

Next week:  Layoffs ala Fairchild

View Entire John East Series

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FPGA Prototyping for AI Product Development

FPGA Prototyping for AI Product Development
by Randy Smith on 06-21-2019 at 8:00 am
Categories: AI, Prototyping, S2C EDA

I recently wrote about The Implications of the Rise of AI/ML in the Cloud. In that article, I wrote about my expectation that the rapidly growing AI market will lead to the accelerated use of high-level synthesis (HLS), prototyping, and emulation. In this article, I will focus on the prototyping portion of that – specifically FPGA prototyping.

As has been noted often recently, the number of Artificial Intelligence (AI) development teams is exploding. While some are in big companies, there are a lot of start-ups as well. But AI differs from many other areas because, it is such a new domain, the things that need to get implemented, such as algorithms, architectures, software, dev ops considerations, etc. are all changing multiple times during the design cycle. How can design teams deal with this, especially the smaller companies with fewer resources?

Emulation boxes are fast, and for an even larger outlay, they can handle design capacities exceeding 2 billion gates. Many start-ups cannot afford those expensive solutions and don’t need quite that capacity. FPGA prototyping offers solid support for several critical functions at a fraction of the cost of emulation hardware. For a small-to-medium sized company, it is a good idea to find a tool for a reasonable price that can handle multiple tasks – more tasks than would typically be handled with an emulation tool. When I looked at S2C’s offering their Prodigy prototyping solutions can be used for design exploration, IP development, hardware verification, system validation, software development, and capability testing. In short, you can use it throughout the hardware design cycle. You can use the same tool in exploring architectural options that you use to validate the functionality of the design. You can also use the same system to develop and the test the software that will run on these devices without having to wait for the final silicon to come back from the factory.

The Prodigy product family also includes ProtoBridge. This product enables the high-speed communications necessary to have a prototyping environment with a transactor interface between software and AXI-compliant hardware. While the system was initially developed with ARM-based systems in mind, it would seem they could easily be used (and probably have already been used) to develop RISC-V systems sporting AXI compliance (such as the SiFive S51). I think this could be very important given the large number of AI teams intending to use RISC-V ISA cores.

My previous article highlighted some AI/ML solutions in the cloud from larger providers in that area – Google, Microsoft, IBM, etc. This is because it is easier to find public information on these offerings since they are available now. But the large and diverse developments at smaller companies is indeed staggering. There are more than 60 startups in the AI market, many of which have already raised $50M or more. While $50M is a lot of money, it doesn’t go very far today if you are designing a chip at one of the newer process nodes. What I am hearing is that developing the AI algorithm in parallel with the chip is quite difficult. These AI algorithms are always under development and yet getting a working prototype before tape-out is critical. Showing a working prototype may also be a critical part of getting the next round of funding. On top of that, just the costs of a new mask set (to fix design flaws that should have been detected earlier) set can kill the company’s dreams. But the creative multifaceted use of FPGA prototyping from a company like S2C can do wonders to stretching that budget.

S2C’s technology is proven. It is trusted by dozens of companies you have heard of, names like Intel, Samsung, Qualcomm, Cypress Semiconductor and LG. AI companies should really give this consideration. S2C pricing starts at under $10,000 for about 10M equivalent logic gates and scales up to much higher capacities.  To get a quick S2C quote click here.

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#56thDAC Discussion on Calibre in the Cloud Brings Sunshine to SOC Developers

#56thDAC Discussion on Calibre in the Cloud Brings Sunshine to SOC Developers
by Tom Simon on 06-20-2019 at 10:00 am
Categories: EDA, Events, Siemens EDA

It was inevitable that EDA applications would meet the cloud. EDA has a long history of creating some of the most daunting compute challenges. This arises from employing current generation chips to design the next generation chips. Despite growing design complexity, many tools have kept pace and even reduced runtimes from generation to generation of process technology.

Mentor’s Calibre is a good example of this, with its annual performance improvements of 25%. Because of that, Mentor’s level of innovation has kept up with the doubling of transistors seen from one node to the next. Naturally designers are glad that turnaround time has held steady over the years. This has been accomplished with foundry assisted rule deck optimization, runtime memory reductions, core engine improvements, and the addition of parallel operations. However, sometimes standing still is not enough.

The cloud presents a huge opportunity to obtain absolute gains in throughput that cannot be realized in any other fashion. However, it is not as simple as launching a few cloud CPU instances and running tools. At the 2019 DAC in Las Vegas, Mentor hosted a four-way presentation about their cloud solution for Calibre. There is no doubt that DRC runtimes can be a bottleneck during the final stages of chip design prior to tapeout. This combined with the accompanying dataset size and computational complexity makes DRC an ideal candidate for cloud based improvements.

The other participants besides Mentor in the presentation were TSMC, Microsoft and AMD. Each of them plays a key role in development of the cloud solution for Calibre. Mentor has made many changes to Calibre to improve efficiency in the cloud. Michael White, Calibre Physical Verification Product Marketing Director, talked about how they worked to make launching cloud-based runs more transparent, by using architectural changes in the way jobs are scheduled and data is transferred to the cloud. Because the cloud can provision extremely large numbers of processor threads, Mentor has exploited every avenue to allow increased parallelization.

Next, we heard from TSMC’s Willy Chen, Deputy Director of Design Methodology & Services Marketing for their Design and Technology Platform. He talked about how on the 10th anniversary of the TSMC Open Innovation Platform (OIP), they worked with Mentor on the “Calibre in the Cloud” project. As part of this this Mentor has joined the OIP Cloud Alliance. This includes a cloud certification process, which focuses on security and creates a legal framework for all the necessary parties to work together.

For the certification process they used a TSMC N5 test chip with Calibre. This design has 500M gates and has a GDS size of 17 GB. The runtime was reduced from 24 hours to 4 hours. This was largely the result of being able to efficiently apply 1024 CPUs as compared to a baseline of 256.

Prashant Varshney, Senior Director, Product Management Azure Engineering from Microsoft spoke about how they looked at every aspect of the chip design process to understand the requirement for each step in terms of memory, CPUs, threading, etc. Using this information, they have mapped each step in the process to specific Azure resources. They also have unique technologies, both in-house and through partnership, for improving cloud performance. Netapp is helping them optimize NFS performance, CycleCompute allows them to bring up 60,000 cores in just 20 minutes. Lastly, AvereNFS helps improve I/O performance with a cloud disk read cache, which is useful for libraries, etc.

The most interesting aspect of the meeting was the AMD presentation. Here we literally see their latest hardware being used to design the next generation of hardware. AMD EPYC processors are used by Microsoft in the Azure Cloud. James Robinson, MTS Silicon Design Engineer at AMD spoke about their experience using Calibre in the cloud. He said that AMD EPYC is well suited for Calibre, with 4 silicon die in each package, containing a total of 32 CPUs that offer 64 threads. There are also 8 DDR4 channels for improved memory support.

Initially the memory requirements for Calibre were prohibitive. However, James observed that Calibre’s per instance memory requirements are reduced as jobs are distributed over greater numbers of processors. He was able to reduce the memory needs so that they fit into available instance types this way. Of course, this offers the added benefit of reduced runtimes. They also learned that it is more efficient to wait to allocate the worker instances until they are needed. Mentor made changes to include this improvement. Mentor gave AMD early cloud-optimized versions of Calibre for testing. James reported that AMD saw a 10 hour run reduced to just over 6 hours.

The takeaway from this presentation was that by combining the efforts of cloud providers, foundries and EDA vendors, significant gains can be made relative to running tools on premises with more limited resources. The cloud can be cost effective because you can literally buy “time”, one of the most valuable commodities for a business. James from AMD pointed out that he was able to apply 4,000 cores to his Calibre runs, which according to him, not even AMD has available on short notice.

After many years it seems that cloud computing for EDA applications is ready and can be an effective tool in increasing productivity. There is more information about Calibre in the Cloud on the Mentor website.

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ARM Spins New IP for Client Applications

ARM Spins New IP for Client Applications
by Bernard Murphy on 06-20-2019 at 5:00 am
Categories: 5G, AI, Arm, IoT, IP
2 Comments

Arm is a machine. They crank out new products in a wide range of categories, Project Trillium for AI, Neoverse for infrastructure, their Automotive Enhanced line and the Pelion IoT platform. And in each they have a regular beat of new product introductions following roadmaps they have already laid out. Not that you’d expect any less from a company in their position. Nevertheless, that they continue to deliver and expand high volume innovation pretty much as they forecast underlines that this is not a company resting on its laurels.

Ian Smythe VP Marketing for the client LOB announced three new IPs last month, directed particularly at mobile devices and the opportunity 5G is creating in those devices. Ian made an interesting point about AI and mobile which I hadn’t realized. I’m generally pretty dismissive about CPU-hosted machine-learning (ML) as the bottom end of the ML hardware hierarchy, but he pointed out that 85% of ~4 billion smart phones are running ML workloads without any dedicated ML hardware assist, using in many cases just CPUs or CPUs plus GPUs. Makes sense – ML hardware on phones is still a pretty new concept and an added cost, so continuing to push CPU-based and GPU-based support for mobile is still very worthwhile.

The first of the IP introduced was the Cortex-A77, building on the A76 architecture but offering a 20%+ advance in instructions-per-cycle performance, still very much targeting smartphone power envelopes and area. Arm sees these devices being particularly helpful in supporting emerging use-cases such as VR/AR/MR (collectively xR) and more advanced ML applications. Ian pointed out an interesting trend in performance for the A-class devices. Arm spent about 4 years, up through around 2016, doubling performance over the A15 but they doubled performance again in the following 2-3 years up to the A77. So they’re accelerating performance improvements while still keeping to mobile client efficiency (power, area) targets.

The next IP up was the Mali-G77. This is also based on an architecture change over the G76, delivering 40% higher performance over that earlier system. This new platform also manages to provide 30% better energy efficiency and 30% better performance density (more performance in a smaller area which is important given the generally large footprint of GPUs in mobile SoCs), along with an improvement in ML performance of 60%. So lower power, smaller area and faster object recognition.

Finally Ian introed the Mali-D77, a second-generation display technology based on their Komeda architecture and targeted particularly to untethered head-mounted displays. This is one of those many domains, almost everywhere, where a general-purpose solution (in this case a GP-GPU) could do the job, but intelligent offloading can do that job so much better. A smaller more dedicated device can do the job of managing display at lower power than the GPU and it can do it faster. The latter is rather important in HMDs because delays between body movement and perceived movement in the display are known to cause motion sickness. So less feeling groggy in your headset and smaller, lighter headsets makes for bad news for your pharmacist and chiropractor but good news for general health.

Ian said that these IPs are available for licensing, early access customers are already designing them into products, and he expects the first of these products to appear in 2020. Good advances, should be a real plus for a fuller mobile 5G experience: gaming, HD video, better voice control and generally more intelligent interfaces on-the-go.

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SiP is the new SoC @ 56thDAC

SiP is the new SoC @ 56thDAC
by Tom Dillinger on 06-19-2019 at 6:48 pm
Categories: Cadence, EDA, Events
3 Comments

The emergence of 3D packaging technology has been accompanied by the term “more than Moore”, to reflect the increase in areal circuit density at a rate that exceeds the traditional IC scaling pace associated with Moore’s Law.  At the recent Design Automation Conference in Las Vegas, numerous exhibits on the vendor floor presented unique packaging options.  Yet, advanced packaging technology also requires corresponding methodology flows, spanning all facets of design, implementation and (electrical plus thermal) analysis.  I had an opportunity to catch up with John Park, Product Management Director for IC Packaging and Cross-Platform Solutions at Cadence, to talk about the flow requirements for these packaging solutions.

Taxonomy – SoC’s, SiP’s, and Chiplets

To start, I asked John for his insights on how to best understand the different terminology used to describe these package offerings.  He began using the image below:

John said, “Multi-chip module (MCM) technology has been around for decades, applied to very specific high-performance computing, communications, and aerospace applications.  The engineering resources to develop the physical implementations were considerable, as was the investment in chip-package-system electrical analysis.”

John continued, “This was followed by two trends.  The ongoing silicon technology scaling of Moore’s Law led to the introduction of system-on-chip (SoC) architectures, integrating IP from multiple sources.  Correspondingly, the signal and power I/O count of these die increased, as well.  The introduction of 2.5D packaging technology, with aggressive interconnect line/space pitch on an interposer (or substrate) enabled these high pin count die to be integrated on a complete system-in-package (SiP).  SiP opportunities have continued to expand.  The introduction of 3D packaging with vertically-stacked die using through-silicon vias (TSV’s) is a recent offering – this technology presents unique constraints to EDA flows, from (limited) pin access for test to different thermal modeling requirements.” 

“I’ve heard a lot recently about chiplets.”, I said.   “What’s a chiplet?”

John replied, “The next trend in SiP design is the integration of heterogeneous chiplets.  It is likely the case that not all functionality in the system needs the PPA characteristics of the same process node.  There may be cost and schedule advantages to the integration of (hard) IP functionality from different sources and technologies – these silicon IP’s are chiplets.  The chiplet I/O’s are simply microbuffers, with an appropriate test wrapper definition.  Chiplets represent a foundry and process node independent disaggregation of the IP in an SoC.  In short, the SiP is the new SoC”.

I asked, “Today, there are some (de facto) architectural definitions for interfacing the IP integrated in an SoC.  How will this extend to a chiplet-based SiP?”

John indicated, “There is a great deal of activity to establish a comparable architectural definition for chiplet based designs – perhaps the best known is the “Advanced Interface Bus” (AIB) specification that Intel has recently provided (license royalty-free).” 

AIB is a parallel bus, clock-forwarded definition for the physical layer interconnect between chiplets, similar to the parallel interface of a DDR DRAM memory module (with single data rate for control signals, double rate for data transfers).  The parallel interface suggests that the connections on the SiP will be “electrically short” and that the available chiplet bumps will be sufficient for parallel bus communications – the additional complexity of SerDes design and the related signal integrity analysis is not required.  Here is a site with more information about AIB, including a download of the specifications (link – registration required for download).

Note that there is also a DARPA program focused on defining a similar IP-chiplet design and reuse platform – “Common Heterogeneous Integration and Intellectual Property Reuse Strategies”, or CHIPS (link).

John added, “There will also be a significant focus on the verification IP (e.g., the verification compliance testbench) for chiplets on an SiP.”

I thanked John for the very lucid description of the nascent chiplet-based design strategy (and for the title of this article).  We shifted gears to discussing how these SiP technologies have impacted EDA tool and flow development.

SiP Reference Flow

The release of a new silicon process design kit (PDK) by a foundry commonly also includes a description of the EDA platform tools that have been qualified for the process node – i.e., the “EDA reference flows”.  John indicated that advanced SiP design kits are also being accompanied by corresponding reference flows.  He described a recent collaboration with TSMC, to provide a comprehensive design and electrical analysis tool suite for TSMC’s advanced (2.5D and 3D) package offerings – e.g., CoWoS, InFO, WoW, and SoIC.  Here  is a list of some of the reference flow tools described in that collaborative announcement, with a few words on their interoperability for SiP designs (link):

Specifically, John focused on the recent enhancements to the OrbitIO interconnect designer.  “The diverse nature of the SiP silicon and package technologies necessitates using different tool platforms.”, John said.  “The methodologies that have been used to manage the overall SiP design tend to be rather ad hoc – for example, spreadsheets exchanged between engineering teams to represent the connectivity between silicon die microbumps, interposer routes/vias, through-silicon vias, and package bumps.  A single, consistent interconnect manager is needed to represent and maintain this model – that is the role of OrbitIO.”

John continued, “OrbitIO provides the SiP model across the platforms used for implementation and analysis of digital die, AMS die, and the package/PCB.  Note that the data representation between OrbitIO and each platform is bidirectional – there is direct integration with the platform to exchange the planning and implementation data.  As additional detail  and/or revisions are made in the specific platform, the updates are reflected in OrbitIO.”

“Are there model connectivity checks available in OrbitIO?”, I asked.  “Sourceless and sinkless pin checks, for example.”

“Yes.”, John replied.  “Further, there are extensions available for customers to develop their own rules and checks.”

There is definitely growing momentum for SiP designs, leveraging advanced 2.5D and 3D packaging technologies.  A significant percentage of those designs will integrate chiplet-level IP – look for standards to emerge for the interconnect fabric (and test methods) between chiplets.  To leverage the packaging technology, a comprehensive EDA strategy is required, to enable planning, implementation, and analysis across different engineering domains as well as to provide a complete, consistent SiP model across tool platforms.  For more information on how Cadence has approached the support for complex SiP’s, please follow this link.

-chipguy

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#56DAC – Functional Safety Panel hosted by Mentor

#56DAC – Functional Safety Panel hosted by Mentor
by Daniel Payne on 06-19-2019 at 5:28 pm
Categories: Automotive, EDA, Siemens EDA

Four experts in the discipline of functional safety were gathered together at #56DAC in Vegas earlier in June, hosted at the Mentor booth, so I rested my legs and typed notes as fast as I could. The product areas that I first think about when functional safety (FuSa) comes up are automotive, medical and aerospace, because keeping human life protected in these areas is paramount. Our moderator was Bryan Ramirez from Mentor, and the panelists included:

The big picture is that automotive safety has gone far beyond just braking and ECUs, think ADAS and Autonomous Vehicles. There are now many new entrants in the automotive electronics space, and they certainly need to quickly learn about about safety practices.

Q: What is the state of the industry for tools to help FuSa requirements?

Ghani – we must meet safety requirements, but how do we achieve that at the system level? With autonomous driving how do we know that with the ML algorithms that it will detect obstacles properly? We need to collaborate in the industry in order to make autos safer. Tools are not complete yet, so there’s progress yes, but problems are growing so fast with AV.

Yves- we need to get suppliers all involved, working together on all ICs, sharing information, sharing IP information while keeping secrets. On the digital side we have good tools for safety, however on the AMS side we need better analysis and tools.

Nir – yes, analog is very complicated. FUSa today is like verification 20 years ago, and the tools are lagging. I really don’t want to wait 20 years to get FuSa tools.

Matt – we now have requirements management, system analysis and verification. Aerospace has many years experience for FuSa, so automotive is still catching up to that level. The tooling not mature yet for functional safety EDA tools and methodology.

Q: What about collaboration aspects?

Matt- to reach autonomous vehicles, safe systems requires collaboration across IP, automotive and systems companies in order to meet ISO 26262 requirements. How will we use these methods and apply new tooling?

Nir – We really need government input in order to meet our safety requirements.

Yves – with new process nodes the safety requirements change, so we need to collaborate with the foundries.

Ghani – within EDA we could use IEEE standards and communications to become safer. We already have Design For Man, DFT and now we need Design For Safety.

Q: How can I know when I’ve tested enough to be safe?

Ghani – well, following ISO 26262 for chip or IP is a minimum starting point, but there is no simple recipe on how to ensure safety in a product. There’s no such thing as complete validation. With safety when human life is in the balance the methodology is to do more verification than before, so it’s going to be company specific.

Yves- that’s a very important question, so the answer is to simulate, verify, then stop, but where is your plan? The plan is the starting point. Did I verify my requirements well? Fault injection simulations are required. Engineering judgement on top of simulation and verification is need, yet we need to go even further.

Nir – I agree, we need to first define our safety goals, then cross checking that we met each safety goal, just like when doing verification.

Matt – when do I know that I’ve verified enough? Has all of my IP been verified up to SoC and system level? Proving that the entire system has been validated is our real goal.

Q: Has my OEM supplier adhered to safety standards?

Matt – integrating each IP needs to fulfill all safety concepts. As each level in the design is completed, validation needs to happen.

Nir – I don’t know that users of our chips can validate what we’ve done internally to meet safety standards.

Ghani – design bugs can be either digital or analog, so how do I know that my verification has covered all of the bugs? At ARM with have used Bus Functional Models along with sensor models to mimic actual behaviors, and it must be highly accurate. Most OEMS just run software on a system, so they only need a high level model of our designs.

Q: How well does requirements get fed through the design chain?

Ghani – we don’t know all of the customer use cases, so we have to make assumptions. If tier 1 and OEMs can share more of what they need, then we could make safer IP blocks.

Yves – requirements need to reach the suppliers very early in the process. It’s not easy to define the requirements for safety. If we don’t get requirements soon enough, then our IP cannot meet expectations.

Matt – exchanging requirements between two different levels is a challenge, although there are multiple formats being used IPDF, Excel, etc., so there’s not a consistent method from top to bottom levels.

Yves – with the ISO 26262 standard we now have the same language to talk with all of our vendors.

My Take

They say that it takes a village to raise a child, and so it is with functional safety, because it will take close collaboration between the systems companies creating each new generation of cars and planes along with all of their suppliers: Foundries, EDA vendors, IP providers. At an annual event like DAC we do get to see all of these companies gathered together at one point in time, and having this kind of a panel discussion is one way to build awareness for our functional safety challenges and approaches.

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Meet the Experts @ ES Design West!

Meet the Experts @ ES Design West!
by Daniel Nenni on 06-18-2019 at 10:00 am
Categories: ESD Alliance, Events, Semiconductor Services

SEMICON West and ES Design West are right around the corner here in San Francisco and I wanted to point out the Meet the Experts segment in the appropriately named Meet the Experts Theater. Great idea really and a super great line-up. The best part of course is actually meeting the experts. Over my 35 year semiconductor career I have traveled more than a million miles and met thousands of the most intelligent people in the world. Never am I the smartest person in the room, not even close, which has made me an excellent listener, absolutely. Even my beautiful wife will tell you that I am a good listener, maybe.

Two more things, my favorite blues musician Aart de Geus has a keynote in the AI Design Forum that you are not going to want to miss and of course the Beyond Hot Party on Tuesday night at Johns Colins Lounge. My wife and I hope to see you there!

Meet the Experts
Tuesday — 10:30am-12:30pm
MORE THAN MOORE: As we reach the limits of scaling geometries, this
session will explore new ways to continue to increase system
functionality while reducing cost and size.
https://bit.ly/2WFsMal

Meet the Experts
Tuesday — 1:30pm-4:30pm
DESIGNING FOR LOW ENERGY: As Smart devices become more ubiquitous,
many have very stringent energy requirements, whether it be very long
battery life or harvesting energy from the environment. This session
will explore how designing for low energy is continuing to evolve with
new design techniques, IP and software solutions.
https://bit.ly/2IgHZL4

Meet the Experts
Wednesday — 10:30am-12:30pm
SILICON DESIGN IN THE CLOUD: As costs both for owning the tools and
the networking infrastructure used for designing (including
verification and modeling) of silicon dramatically increase, companies
are increasingly looking for cloud-based solutions on which to do
their silicon design. This session will chart the current and future
of such cloud-based design from the perspective of silicon design tool
users, developers of such tools, and cloud solution providers.
https://bit.ly/2WBNoQU

Meet the Experts
Wednesday — 1:30pm-4:30pm
MACHINE LEARNING, AI, AND EDA: From EDA tools to voice and image
recognition, machine learning and AI are increasingly important for
both the design and the design process. This session will explore the
impact on applications and tools.
https://bit.ly/2Iygrje

Meet the Experts
Thursday — 10:30am-12:30pm
SECURITY: With SoCs increasingly used in critical applications, and
more of the system software being integrated onto those chips,
hardware and software security becomes increasingly critical for
designers. Speakers will discuss security concerns and risks in
today’s designs.
https://bit.ly/2MH4VY7

Meet the Experts
Thursday — 1:30pm-4:30pm
ADVANCED APPLICATIONS: From DSP and media processing through changing interface standards, SoCs continue to increase in complexity. This
session will explore tools and methodologies to develop these complex
chips, along with advanced verification methodologies to assure
correctness.
https://bit.ly/31s0R1o

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Synopsys Low Power Workshop Offers Breadth and Depth

Synopsys Low Power Workshop Offers Breadth and Depth
by Bernard Murphy on 06-18-2019 at 5:00 am
Categories: AI, Automotive, Events, Synopsys

Synopsys seems to particularly excel at these events, whether in half-day tutorials at conferences or, as in this case, in a full-day on-site workshop. You might think there’s not much that can be added in this domain, other than to bring low-power newbies up to speed, but you’d be wrong. This event set the stage with surveys on needs in power management and verification (maybe this was for the newbies but good to recap), a detailed look at implementation aspects, the emerging importance of pre-RTL UPF checks, a very enlightening discussion on the scalability of UPF for large designs (hint – this is a problem) and a discussion on on-going work to attack that problem.

Power verification, optimization

There were also a couple of customer presentations, one from Intel and HYGON. In deference to the wishes of both companies I won’t discuss their presentations. I also won’t cover every Synopsys presentation to keep this blog to a manageable size.

Low Power Trends

Sridhar Seshadri (VP and Chief Architect at Synopsys) opened with an overview. Their customer verification surveys show low-power verification neck-and-neck with debug as the top verification concerns in 2018. Initiatives they have to manage the need include software-driven power analysis and signoff power closure. Mostly well-known flows here: ZeBu and Virtualizer for early analysis, ZeBu and PrimePower for peak and average analysis on RTL, and PrimePower and RedHawk for power and IR-drop signoff.

Mary Ann White (Dir Marketing in Synopsys DG, also an ISO 26262 functional safety practitioner) presented results from their customer survey, showing for example that while timing closure, timing and area goals and on-schedule tapeout lead all other concerns by a 2X+ margin, power concerns follow right behind. One very interesting insight was a side-by-side comparison of mobile and automotive expectations. In order of mobile and automotive:

    • process – 28nm to 7nm versus 180nm to 7nm
    • design size (instances) – 100M+ in both cases
    • frequencies – up to 4.2GHz versus up to 77GHz
    • voltages – 0.5 to 1.8V versus 1 to 60V
    • temperature – 0 to 40 degrees versus -40 to 150 degrees
    • expected lifetime – up to 3 years versus up to 15 years
    • target field failure rate – <10% versus zero

Automotive has caught up on process and size, is ahead on frequency, a wider span on voltage, and unsurprisingly more demanding on temperature, lifetime and failure rates.

Progress in Implementation

Mary Ann mentioned a number of power saving techniques available in the Synopsys implementation flow, including concurrent clock and data optimization, intelligently relocation ICG gates closer to the driver, more multi-bit banking and de-banking support, low power restructuring in DC NXT and in fusion between ICC II and synthesis, optimization in PT and ICC II for ultra-low voltage operation and optimizations in power recovery at signoff by downsizing or swapping cells on Vth. Each of these is delivering meaningful improvements in dynamic and/or leakage power savings.

Viswanath Ramanathan introed support for multiple power domains in a single voltage area with a couple of examples. I’m not going to butcher his technical explanation here – contact Synopsys for more detail.

UPF Scalability for SoC

Harsh Chilwal (PE at Synopsys) gave a fascinating and somewhat concerning presentation on the scalability of UPF. We all know that designs are getting bigger and so of course UPFs are getting bigger. What may be less apparent is how quickly at the SoC level UPFs are getting bigger and more costly to compile, at seemingly a super-linear rate even on a log-scale of UPF complexity. Harsh told us that this is the nature of the beast, mapping essentially flat Tcl (the foundation under UPF and most things EDA) onto structural RTL. This can only happen effectively after the design is resolved and can amount to 4X+ of total elaboration time for a VCS simulation.

Flexible though UPF is, that flexibility often fights efficiency. Loading UPF files (sometimes many nested files) for every relevant instance creates zillions of UPF objects, chewing up compile time and memory. Transitive find commands, beloved by many users for their adaptability, create huge strings which can easily overflow in a good-sized SoC and are correspondingly expensive in time and memory (blame Tcl, not UPF for that). Path-tracing, needed again for adaptability, can equally be hugely expensive in an SoC if not carefully bounded. These and other factors highlight the challenging tradeoffs between ease of use and practical bounded use in UPF-based applications.

Harsh suggested a number of methodology best practices to avoid or at least mitigate some of these problems, for example using wildcards rather than find_objects and using soft or hard macro attributes to identify IPs and thereby bound path-tracing. He also suggested using power models to make the UPF modular rather than flat and bind those models to the RTL, avoiding a lot of redundancy. He also talked about some forward-looking work they are doing on hierarchical compile as a way to break free of the flat UPF paradigm.

Kaushik De (Scientist at Synopsys) followed with an abstraction approach, a likely unavoidable tradeoff as designs and UPFs continue to grow. For this purpose, they define a signoff abstract model (SAM) which he positions as similar to a flat model, minus the things you don’t need to know (the devil is no doubt in those details); they have mechanisms to create, write and read SAM models. Kaushik also showed customer stats with significant run-time and memory improvements exploiting SAM-based flows.

The trick with hierarchical analysis is to ensure you can trust that nothing falls through the hierarchical cracks. He showed a couple of approaches they use to build confidence in the validity of the SAM-based analyses. Each compares abstracted analyses with full-flat analyses to ensure no violations are lost. Any disconnects are used to refine the SAM models I presume. I understand that customers using these flows today do the both analyses and comparison on an initial run, then use hierarchical analysis for subsequent runs, perhaps adding a full-flat run at the end for security.

Machine Learning in Low Power

It’s happening everywhere else; no surprise ML should appear here also. Mary Ann first talked about ML optimization for PrimeTime power recovery, achieving run-time speedups of between 4X and 10X. This is a supervised learning approach I was told. You, the customer, first train the system then can use that training on subsequent designs.

Kaushik talked about accelerating debug using machine learning. This I thought was a very cool application since it builds on unsupervised learning to identify clusters of related problems, unlike many ML applications which rely on supervised learning to identify specific object matches. This is particularly useful in static UPF analysis which can generate hundreds of thousands of errors. But there aren’t really anywhere near that many root-cause bugs; instead each real bug spawns many symptoms. Using unsupervised learning (with no doubt a good deal of secret sauce) can massively reduce the debug effort. Kaushik showed one example, resulting from a level-shifter error, where a huge number of reported errors and warnings could be traced back to just two problems. Way easier than the traditional approach.

You can learn more about what Synopsys is doing in low-power HERE.

 

 

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An Update from Joe Sawicki @ Mentor, a Siemens Business 56thDAC

An Update from Joe Sawicki @ Mentor, a Siemens Business 56thDAC
by Tom Dillinger on 06-17-2019 at 10:22 pm
Categories: Siemens EDA

Executives from the major EDA companies attend the Design Automation Conference to introduce new product features, describe new initiatives and collaborations, meet with customers, and participate in lively conference panel discussions.  Daniel Nenni and I were fortunate to be able to meet with Joe Sawicki, Executive Vice President of the IC EDA segment at Mentor, a Siemens business, for a brief update.  Here are some of the highlights of our discussion.

Machine Learning in EDA

There were numerous technical sessions and EDA vendor floor exhibits relating to opportunities to incorporate machine learning algorithms into design automation flows.  Joe shared some examples where ML is being integrated into Mentor products:

  • Calibre Litho Friendly Design (LFD)

Lithographic process checking involves evaluating a layout database for potential “hotspots” that may detract from manufacturing yield.  Although conventional design rule checking will identify layout “errors”, there remains a small, but finite, probability that a physical design may contain yield-sensitive topologies at the edges of the litho process window.  Traditionally, lithographic process checking utilized a detailed litho simulation algorithm applied to the layout database – a “model-based” approach.

However, that method has become computationally intractable at current process nodes.  Instead, a “fuzzy” pattern matching technique was pursued, using a set of “hotspot-sensitive” layout patterns provided in the foundry PDK.  A set of “rule-based” checks were applied using these patterns.  More recently, a mix of model-based and rule-based techniques are used, where a subset of patterns find layout structures to direct to the litho simulation tool.  Yet, pattern identification is difficult.  It relies upon the (growing) database of hotspot identification, and a judicious selection of the pattern radius – too large a pattern will result in fewer matches and poor coverage, too small a pattern will identify many unnecessary hotspots for simulation.

Joe indicated, “Machine learning technology has been integrated into the Calibre LFD tool, to better distinguish which pattern structures are potential litho risks using training set learning.” 

The figure below depicts a deep neural network applied to the binary classification of design patterns to direct to litho simulation (from the Mentor whitepaper:  Elmanhawy and Kwan, “Improve Lithographic Hotspot Detection with Machine Learning”).

Pattern matching and litho simulation rely upon an existing database of known hotspots.  Using a deep neural network, using hotspot and non-hotspot training data, the ML-based approach in Calibre LFD predicts additional yield detractors in new layout, beyond the pattern set in the PDK.  Very cool.

  • Calibre mlOPC

Joe continued, “We are also incorporating ML technology into the Calibre products used directly by the fabs.  There is a wealth of metrology data taken during fabrication.  We are applying pattern decomposition and classification on this data to provide feedback to the process engineering team, for process line tuning/centering and for optical mask correction algorithms.”

  • Tessent Diagnosis

Lastly, Joe described how ML methods are being applied in the area of fault diagnosis.  He indicated, “Mentor has led in the introduction of cell-aware test, where additional circuit node and parametric fault candidates within cells are presented to the test pattern generation and fault simulation tools.  We have incorporated ML inference techniques within Tessent Diagnosis to correlate test fail data, and provide improved cell-internal diagnostics to the physical failure analysis (PFA) engineering team.” 

There’s no doubt that ML technology will offer EDA developers new techniques for inference classification in analysis flows (and potentially, new approaches to non-linear optimization algorithms in design implementation flows).

 

Automotive System Verification and Digital Twin Modeling

There continues to be synergistic product developments within Siemens, leveraging the IC design and verification technology from Mentor.  (I presume any questions about the motivation behind the Mentor acquisition by Siemens have long since been answered.)

Joe described a recent Siemens announcement – the “PAVE 360” initiative – which provides a comprehensive (pre-silicon) verification platform for simulation of an automotive environment.

Joe said, “With the Veloce Strato emulation system, we have the capability and capacity to provide a digital twin of the automotive silicon design, the embedded software, the sensor/actuator systems, and the surrounding traffic environment into which the ADAS or autonomous vehicle is placed.  This includes both the deterministic and predictive (ML-based) decision support within the model.”

Joe also reminded us, “A digital twin environment is used not only for pre-silicon verification – it is also the debug platform to analyze field data.  Testing of autonomous driving solutions will uncover issues, providing engineers with an accident database.”

The ISO26262 standard for autonomous vehicles mandates a closed-loop tracking system that demonstrates how these issues have been addressed and subsequent verified.  The PAVE 360 digital twin platform is the means to provide that qualification.

The overall goal of the Siemens PAVE 360 platform is to provide a verification reference solution across the breadth of automotive sub-system suppliers.  A number of demonstration labs have been established worldwide, providing suppliers with access to the platform – see below.

More info on the PAVE 360 initiative is available here.

Photonics

In our remaining minutes, Joe highlighted another recent Mentor announcement, focused on accelerating the design and verification of silicon photonics layouts.  Conventionally, layout design consisted of placement of cells from a photonics library, followed by manual custom layout generation of the “waveguides” between the cells (and the related electrical signals that modulate the waveguides).  There are strict constraints on the length and curvature of the guides to minimize dispersion – photonic layout design has required specialized layout expertise.

Joe described the new LightSuite Photonic Compiler platform, developed with collaborative support from Hewlett-Packard Enterprise.  The compiler provides automated generation of the waveguide layouts and connections, as well as the surrounding electronic component interconnects.  The figures below illustrate the overall compiler flow, as well as an example where the electrical connectivity is critical to the proper waveguide function.

The curvilinear nature of photonic structures necessitates exacting design rule descriptions.  Calibre has been extended to support “equation-based” design rules in the foundry’s photonics PDK.  Calibre RealTime Custom is exercised within the LightSuite Compiler to ensure the waveguide (and electronic) interconnects are DRC-clean.

Joe indicated, “To date, photonics design has required specialized expertise, utilizing a full-custom methodology.  The automation now available offers capabilities that will enable faster implementation.  Designers will now be able to do what-if optimizations that were previously extremely difficult.”  Mentor quoted a design example with 400 optical and electric components placed, routed, and DRC-verified in 9 minutes with the LightSuite Photonic Compiler.  More info on LightSuite is available here.

Although brief, the discussion that Daniel Nenni and I had with Joe S. was enlightening.  Machine learning-based classification and optimization approaches to EDA algorithms are well underway, with many more applications to come.  Digital twin verification platforms will enable (multiple vendor) subsystems to interact in a replica of a complex external environment, both in pre-silicon validation and post-silicon debug.  The opportunities for local, high-speed signal interfacing using integrated silicon photonics are great, but their progress has been hampered by the need to employ a full-custom methodology – improved automation flows will no doubt accelerate this market segment.  Occasionally, I find myself thinking, “Oh, there probably won’t be much new at DAC this year.” – then, when at the conference, I never cease to be amazed at the ongoing innovations in the EDA industry.

-chipguy