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Free webinar – Accelerating data processing with FPGA fabrics and NoCs

Free webinar – Accelerating data processing with FPGA fabrics and NoCs
by Tom Simon on 10-14-2019 at 10:00 am

FPGAs have always been a great way to add performance to a system. They are capable of parallel processing and have the added bonus of reprogramability. Achronix has helped boost their utility by offering on-chip embedded FPGA fabric for integration into SoCs. This has had the effect of boosting data rates through these systems… Read More


Response to IP’s Growing Impact On Yield And Reliability

Response to IP’s Growing Impact On Yield And Reliability
by Daniel Nenni on 10-14-2019 at 6:00 am

One of the reasons I founded SemiWiki nine years ago was the lack of EDA, IP and Foundry content in the media. The problem is that unless you work in the industry it is very difficult to write about it in competent technical detail. Most media outlets only know what vendors tell them which is how the semiconductor industry worked before… Read More


Accellera IP Security Standard: A Start

Accellera IP Security Standard: A Start
by Bernard Murphy on 10-10-2019 at 5:00 am

I mentioned some time ago (a DVCon or two ago) that Accellera had started working on a standard to quantify IP security. At the time I talked about some of the challenges in the task but nevertheless applauded the effort. You’ve got to start somewhere and some way to quantify this is better than none, as long as it doesn’t deliver misleading… Read More


Functional Safety ARC Processor IP will speed automotive system design

Functional Safety ARC Processor IP will speed automotive system design
by Tom Simon on 10-09-2019 at 10:00 am

In the automotive space you can’t even get out of the starting gate without Functional Safety (FS). All electronic system that go into cars must have ISO 26262 certification. However, this is not something you slap on after the fact. From the ground up the requirements for ISO 26262 must be considered and the proper processes must… Read More


Webinar – AI/ML SoC Memory and Interconnect IP Perspectives

Webinar – AI/ML SoC Memory and Interconnect IP Perspectives
by Tom Simon on 10-08-2019 at 10:00 am

For decades development work on Artificial Intelligence (AI) and Machine Learning (ML) was done on traditional CPUs and memory configurations. Now that we are in the “hockey stick” upturn in deployment of AI and ML, the search is on for the most efficient types of processing architectures. The result is a wave of development for… Read More


SiFive Continues to Foster RISC-V in the Middle East With Tech Symposiums

SiFive Continues to Foster RISC-V in the Middle East With Tech Symposiums
by Swamy Irrinki on 10-05-2019 at 8:00 am

Workshops Coming to Istanbul, Amman, Cairo and Abu Dhabi

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SiFive is continuing its tour through the Middle East with highly educational RISC-V Tech Symposiums and Workshops in the key locations of Istanbul, Amman and Cairo. These cities are some of the most technologically advanced in the region, and we are eager … Read More


Synopsys and Infineon prepare for expanding AI use in automotive applications

Synopsys and Infineon prepare for expanding AI use in automotive applications
by Tom Simon on 10-03-2019 at 10:38 am

We all know that cars are using processors for many tasks, but it is easy to fail to comprehend just how many there are in a typical modern car. Browsing through the Infineon AURIX automotive processor application guide, you can start to see just how pervasive processors are. The AURIX processors are specifically designed for automotive… Read More


How Should I Cache Thee? Let Me Count the Ways

How Should I Cache Thee? Let Me Count the Ways
by Bernard Murphy on 09-25-2019 at 5:00 am

Caching intent largely hasn’t changed since we started using the concept – to reduce average latency in memory accesses and to reduce average power consumption in off-chip reads and writes. The architecture started out simple enough, a small memory close to a processor, holding most-recently accessed instructions and data … Read More


AI Inference at the Edge – Architecture and Design

AI Inference at the Edge – Architecture and Design
by Tom Dillinger on 09-23-2019 at 10:00 am

In the old days, product architects would throw a functional block diagram “over the wall” to the design team, who would plan the physical implementation, analyze the timing of estimated critical paths, and forecast the signal switching activity on representative benchmarks.  A common reply back to the architects was, “We’Read More


Glasses and Open Architecture for Computer Vision

Glasses and Open Architecture for Computer Vision
by Bernard Murphy on 09-18-2019 at 6:00 am

You know that AI can now look at an image and detect significant objects like a pedestrian or a nearby car. But had you thought about a need for corrective lenses or other vision aids? Does AI vision decay over time, like ours, so that it needs increasing help to read prescription labels and identify road signs at a distance?

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