Part 4 of this series discussed how a transistor Extension could be fabricated in a planar device without using an implant operation, and is instead formed using a preferential etch followed by a selective epitaxial deposition. This final installment of the series will present the formation of an Extension in a FinFET transistor using the same etch and deposition methodology.
As in the planar case, this technique for fabricating an Extension region depends on etching out a precisely formed cavity adjacent to, and on both sides of, the transistor channel region. Also, like the planar case, this cavity etch is performed as part of the replacement Source/Drain etch that takes place prior to the epitaxial deposition of the SiGe compressive stressor. However, in the case of a FinFET, the Extension cavity is formed as part of the fin removal process.
Figure #1 illustrates PMOS and NMOS fins just prior to the Source/Drain cavity etch and the formation of the SiGe stressor crystals. The NMOS fins are coated in a protective hard mask. (Note that the PMOS fins are located in the N-Well and the NMOS fins are located in the P-Well.)
The process begins by etching away the PMOS fins located outside of the gate electrode. This is accomplished by first etching away the thin coating of oxide (left on the on the top of the fins after the sidewall spacer etch), and then etching away the Silicon fins using a wet etch of NH[SUB]4[/SUB]OH. Alternate etch chemistries that will also work for this task are NH[SUB]3[/SUB]OH, TMAH, KOH, NaOH, BTMH or amine-based etchants.
Once the fins are removed, the nitride spacers along the fin sidewalls will collapse and they can be easily removed from their attachment points to the Gate Electrode nitride spacer. The result of this etch is illustrated in figure #2.
Figure #2 displays the device structure after the PMOS fins have been removed. The TMAH etches preferentially into the N-Well forming the characteristic “V” shaped groove that self-limits the etch process. Perpendicular to this groove, and along the (111) plane, the TMAH etches the silicon fin more slowly and forms the Extension cavity beneath the Gate Electrode spacer. Figure #3 displays a close-up view of the Extension cavity.
Following the etch, a selective deposition of SiGe takes place. This operation will deposit SiGe only on the exposed silicon surfaces which restricts the deposition to the silicon in the V-shaped groove and the Extension cavity as displayed in figure #4.
The Gate Electrode in figure #4 has been made transparent in order to make the Extension structure visible. Figure #5 is a close up of the Extension structure that is located beneath the Gate Electrode spacer.
So is this technique for forming the transistor Extension actually being used?
Figure #6 displays a Transmission Electron Micrograph of an Intel 22nm PMOS FinFET gate array.
The TEM preparation of this image makes it initially difficult to understand. It is a dark-field image so the denser materials appear lighter and the view is top-down and the Gate Electrodes have been polished back to the tops of the SiGe crystals. As a result of this polish, the Gate Electrodes no longer wrap around the top of the fins but are located on either side of them. This reveals the transistor channels and the Extensions located on either side of the channels.
As the TEM illustrates, the SiGe crystals extend behind the nitride spacers and slightly into the channel region to form the transistor Extensions. Based on this evidence it would appear that the technique described in this paper has been in use for some time.
Forming the transistor Extensions as part of the fin removal and SiGe deposition process offers a number of important advantages. First, it is a simpler process. It eliminates all of the implant steps required of other Extension formation methodologies and their associated photo-masking operations. More importantly, it provides a robust solution for effectively forming transistor Extension regions even with the very tight Gate Electrode pitches found at the 10/7/5nm nodes.
This technique would require careful control of the fin removal etch to ensure that the Extension cavity is formed to the correct dimensions, but the advantages provided by this method far outweigh any disadvantages.
This content was authored by Jerry Healey of Threshold Systems Inc. For detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.