The problem of traditional FinFET Extension Implant doping concerns the awkward 3-dimensional structure of the fin. Because the Extension Implant defines the conductive electrical pathway between the Source/Drains and the undoped channel portion of the fin, it is essential that the fin be uniformly doped all three of its surfaces (the two sides and the top of the fin). The use of a short Amorphous Carbon implant mask helps enormously with this implant because is enables a steep +/- 30º implant angle that allows more of the dopant to be retained on the fin as discussed in part one of this series (refer to figure #1).
Implanting the fin with such a steep double implant allows each side of the fin to be adequately doped, but has the disadvantage that the top of the fin experiences both of these implants (refer to figure #2). This means that the top of the fin is doubly doped and becomes the most conductive fin element. This results in non-uniform fin conductivity that adversely affects transistor performance.
An alternative doping methodology that results in uniform doping on all three sides of the fin is required. This task can be accomplished with two additional masking and implant steps, a nitride deposition and etch operation, followed by a selective oxidation.
The process begins with a masking operation that covers up the N-Wells and exposes the NMOS devices located n the P-Wells. This is followed by an Arsenic implant at 90 degrees into the NMOS fins. (refer to figure #A). This will dope the top of the NMOS fins. However, because the fins are very vertical at the 14/10nm nodes, very little if any dopant will be implanted into the fin sidewalls.
Next, the photoresist is stripped and new photoresist is patterned that covers the P-wells and exposes the N-Wells where the PMOS transistors are located. A 90 degree Boron implant followed by a Carbon locking implant dopes only the top of the PMOS fins (refer to figure B).
Next, a thin nitride layer is blanket deposited across the wafer using Atomic Layer Deposition (refer to figure C). The nitride layer is then etched in a highly anisotropic etch that forms nitride spacers on the gate electrodes and the fins. This is followed by a mild oxide etch that removes the thin layer of oxide on top of the gate electrodes and the top of the fins and exposes the underlying silicon in these areas (refer to figure D).
The wafers then undergo an oxidation step. The Nitride acts as an oxygen barrier and prevents oxide from growing on the surfaces that it covers. However, on the exposed surfaces (the top of the fins and the top of the Gate Electrode) a thick layer of oxide grows (refer to figure E). This thick layer of oxide will act as an implant mask in the following Extension implant operations.
The nitride layer is then stripped from the wafer (refer to figure F). This step is followed by the deposition and patterning of a hard mask that after patterning will cover the N-Well and expose the NMOS devices in the P-Well.
The Extension implants for the NMOS devices are then conducted as illustrated in Figure #3.
However, since the top of the fins are now covered in a thick oxide, only the sidewalls of the fins will experience the +/- 30 degree double implant. This is because although the dose of the Extension implant is very high (10[SUP]15[/SUP] ion/cm[SUP]2[/SUP]), the energy of this implant is very low. The dopant from this implant will be able to penetrate the thin oxide along the sidewalls of the fin, but not the thicker oxide at the top of the fin (refer to figure #4).
The Extension implant is then repeated for the PMOS fins using Boron and Carbon.
This methodology ensures that the fins experience a uniform Extension implant across the top and on both sides of the fin and avoids the double implant of the fins on their upper surfaces that is common in more conventional implant schemes. However, such uniform fin doping is accomplished at the expense of significantly greater processing.
For more information on this topic and for detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.