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The Answer to Why Intel PMOS and NMOS Fins are Different Sizes

The Answer to Why Intel PMOS and NMOS Fins are Different Sizes
by Daniel Nenni on 04-08-2019 at 7:00 am

Like many others, we have often wondered why the PMOS fins on advanced microprocessors from Intel are narrower than the NMOS fins (6nm versus 8nm). This unusual dimensional difference first occurred at the 14nm node and it coincided with the introduction of Solid State Doping (SSD) of the fins at this node.


We have concluded that the difference in fin dimensions occurs as a consequence of the SSD process. In the SSD process the PMOS fins experience a total of five etch operations whereas the NMOS fins experience only two etches. Each of these etches, especially the ones to remove the Boron doped glass, will require a slight silicon etchant to ensure complete removal of the doped glass from the surface of the fins. Each of these etches will also result in a slight thinning of the silicon fins.

As a consequence of the PMOS fins receiving five etches to the NMOS fins two etches, the PMOS fins are slightly thinner than the NMOS fins.

The SSD process begins after the P-Well and N-Well formation and the fin etch. These operations are followed by the deposition of thin 5nm layer of Boron doped glass. The P-Well is then masked and the Boron doped glass is etched away from the N-Well region (refer to Figure #1). This etch will involve a slight silicon etch that will thin the PMOS fins slightly. The NMOS fins will not see this etch (recall that the PMOS transistor fins are located in the N-Well and that the NMOS transistor fins are located in the P-Well).

The PMOS and NMOS fins are then encased in a thick layer of oxide that is then CMPed and etched back to the boundary between the undoped portion of the fin and the well (refer to Figure #2). This is the first etch that the NMOS fins experience and the second fin etch seen by the PMOS fins. However, because this etch is mainly removing only undoped glass it is unlikely to thin the silicon fins.

The wafers are then annealed to drive the Boron into the P-Well along the lower edges of the fins. The Boron glass has been removed from the N-Wells so they do not see this extra dopant.

All of the glass is then removed from the fins including the layer of Boron doped glass along the base of the P-Well (refer to Figure #3). This is the second etch that the NMOS fins experience and the third etch seen by the PMOS fins. Since Boron doped glass is being removed this etch will also slightly etch both the PMOS and the NMOS fins.

Next, a double layer of oxide (2nm thick) and a layer of SiON (2nm thick) is deposited across the wafers. The P-Well is then masked and this double layer is removed from the N-Well. This operation is followed by the deposition of a 5nm layer of Phosphorus doped glass.

A thick layer of undoped glass is then deposited that encases the fins. This oxide is polished and then etched back to the boundary between the undoped portion of the fin and the well (refer to Figure #4). During this etch Phosphorus doped glass is removed from the undoped portion of both the PMOS and the NMOS fins down to the Well boundaries. However, the NMOS fins are still covered in a protective double layer of oxide + SiON and do not experience this etch. Since these protective layers have been removed from the PMOS fins they fully experience this etch and are thinned as a result. This is the fourth PMOS fin etch.

The wafers are then annealed to drive the Phosphorus dopant into the N-Well along the edges of the fins. The P-Well does not experience this dopant drive because the thin protective layers of oxide + SiON shield the P-Wells from any dopant diffusion.

All of the oxide (doped and undoped) is then removed from between the fins (refer to Figure #5). The NMOS fins are still protected by the thin layers of oxide + SiON so they do not experience this etch. However, the PMOS fins do experience this etch and it will thin them. This is the fifth PMOS fin etch.

Finally, two thin layers of oxide + SiON are deposited, followed by a thick layer of STI oxide. The STI oxide and the thinner layers of oxide + SiON are etched down to the undoped fin/well boundary leaving behind STI oxide between all of the fins. Since this etch is removing undoped glass the fins will be unaffected.

So the difference in the dimensions of the PMOS and the NMOS fins occurs as a result of the fact that the SSD process causes the PMOS and the NMOS fins to experience a different number of etch operations that are designed to remove doped glasses.


For more information on this topic and for detailed information on the entire process flows for the 10/7/5nm nodes attend the course “Advanced CMOS Technology 2019” to be held on May 22, 23, 24 in Milpitas California.

https://secure.thresholdsystems.com/Training/AdvancedCMOSTechnology.aspx

Written by: Dick James and Jerry Healey