RVN! 26 Banner revised (800 x 100 px) (600 x 100 px)

How can Semiconductor Manufacturers add new Capacity to Meet Demand as Quickly as Possible?

How can Semiconductor Manufacturers add new Capacity to Meet Demand as Quickly as Possible?
by Daniel Nenni on 07-19-2021 at 10:00 am
Categories: Atonarp, Events, Semiconductor Services

The causes of the chip shortage crisis have been widely discussed, but what about specific solutions? How can semiconductor manufacturers add new capacity to meet demand as quickly as possible?

While there is a lot of talk about investment in building new chip plants, these traditional methods of manufacturing capacity growth typically take several quarters, or even years, to come to fruition. Building new fabs is a monumentally costly and time-intensive task requiring years of planning and construction, which means new fabs realistically are not going to fill the short-term or medium-term gap. Likewise, adding more processing equipment is capital-intensive, takes many quarters to realize, and is often limited by scarce clean-room floor space and equipment lead times that can be 6-12 months or longer.

We instead must look for smarter, creative ways to increase throughput and yield, so more chips can be produced in the fabs we already have, without requiring lengthy building or equipment facilitation.

Which brings us to an upcoming webinar in partnership with Atonarp:

WEBINAR: A review of new in-situ metrology for advanced semiconductor processes

In the webinar, Atonarp will detail Aston-based improvements in FAB throughput, as well as in-situ metrology solutions for advanced CVD and etch applications. The benefits of Aston’s robust molecular sensor technology with integrated plasma ionization source will be compared with existing legacy metrology solutions, such as residual gas analysis and optical emission spectroscopy.

Aston’s ability to respond to a range of metrology application challenges will be reviewed and discussed, including PE-CVD end point detection, dry pump management, Atomic Level Deposition (ALD), advanced high aspect ratio, and small open area etch and advance chamber management.

The speaker is Saïd Boumsellek – Sr. Director, Instrumentation & Applications Atonarp. At Atonarp, Saïd has taken on the role of leading the development of Instrumentation and Applications of mass spectrometry products. A major initiative is to drive an externally focused application development strategy by working directly with market leaders in semiconductor process control.

Prior to Atonarp, Saïd served as the Director of Advanced Technology at L3 Security Detection Systems, where he led the R&D team. Saïd holds a PhD in Physics, has a long track record in instrument development and deep domain expertise in the chemical analysis industry. He has held many professional roles including Member of Technical Staff at Caltech’s Jet Propulsion Laboratory developing miniature charged particle analyzers for planetary exploration.

Saïd has prepared over 100 research proposals and secured $15M+ in R&D funding from various U.S. Government agencies. He authored over 32 publications in peer-reviewed journals, and 40+ patents in the areas of ionization sources and chemical analysis technologies.

About Atonarp
Atonarp is leading the digital transformation of molecular sensing and diagnostics for life sciences, pharmaceutical, and semiconductor markets. Powered by a unifying software platform and breakthrough innovations in optical and mass spectrometer technology, Atonarp products deliver real-time, actionable, comprehensive molecular profiling data. Led by a world-class team of experts in the development and commercialization of semiconductor, life sciences, and health diagnostic instruments, Atonarp has operations in Japan, the United States, and India. Learn more at https://atonarp.com.

I hope to see you there!

July 19, 2021April 20, 2022

VLSI Technology Symposium – Imec Alternate 3D NAND Word Line Materials

VLSI Technology Symposium – Imec Alternate 3D NAND Word Line Materials
by Scotten Jones on 07-19-2021 at 6:00 am
Categories: Events, Semiconductor Services, TechInsights
2 Comments

At the 2021 VLSI Technology Symposium, Imec presented on Ruthenium (Ru) and Molybdenum (Mo) as alternate Word Line (WL) materials for 3D NAND Flash “First Demonstration of Ruthenium and Molybdenum Word lines Integrated into 40nm Pitch 3D NAND Memory Devices”. I had an opportunity to interview one of the authors: Maarten Rosmeulen.

The current state of the art in NAND Flash memory is 3D NAND with ever increasing number of layers, for example at the same conference Samsung presented their forthcoming 176-layer 3D NAND process that is a follow up to their 128-layer process. One notable aspect of the Samsung announcement was that they reduced the height of their memory cells for the 176-layer process to control the height of the overall memory stack. Micron and SK Hynix have also announced 176-layer processes and Kioxia has announced a 162-layer part following their 128, 128 and 112-layer processes, respectively.

As the layer count increases, there is pressure to shrink the layer thicknesses to control the height of the stack for patterning and stress reasons as Samsung has done for their 176-layer process. The most prevalent type of 3D NAND in the industry is Charge Trap flash using a replacement metal gate (RMG) process. In the RMG process, alternating layers of oxide and nitride are deposited, the nitride is a sacrificial film that is later removed and replaced with the metal gate and a metal sheet that serves as the word line, see figure 1.

Figure 1. Replacement Metal Gate Process.

Currently the word line material of choice is Tungsten (W).

The resistance of a conductive line is given by:

R = ρL/A,

where ρ is the resistivity, L is the length and A is the cross-sectional area.

As the nitride layer thickness is reduced, the resulting replacement metal sheet is getting thinner reducing the cross-sectional area and at small dimensions ρ increases due to electron scattering further compounding the increase in resistance. Increases in word line resistivity lead to slower program/erase times for the product.

The degree to which the resistivity increases at small dimensions is partially determined by the electron mean free path in the material. The increase in resistivity at small dimensions can result in materials with relatively higher resistivity in bulk having lower resistivity at small dimensions. A figure of merit for materials at small dimensions is the bulk resistivity multiplied by the electron mean free path. Figure 2 presents some data on material resistivity.

Figure 2. Alternate Word Line Material Resistivity.

From figure 2 both Mo and Ru will have potentially lower resistivity at small dimensions than W. Of course, the values in figure 2 are just bulk values and do not necessarily translate to actual devices structures and the purpose of this work is to experimentally measure the performance.

In this work a five-layer device was created to evaluate the resistivity and transistor performance with these alternate materials. Because Imec is a research facility it is not feasible for them to create 176-layer devices, but the 5-layer device preserves the essential physics.

Figure 3 presents the resistivity of Mo and Ru for WL with thicknesses of 35nm, 25nm and 20nm. Ru shows lower resistivity than Mo in all cases studied.

Figure 3. Word Line Resistivity.

Figure 4 presents Mo transistor performance and it is better than Ru (not shown).

Figure 4. Mo Transistor Performance.

Figure 5 compares program erase for Mo and Ru and Mo shows faster program/erase than Ru.

Figure 5. Program Erase.

Finally, figure 6 compares retention for Mo and Ru, Ru is better than Mo but Mo performance is very close.

Figure 6. Retention.

Comparing the performance, Ru is better for resistivity and Mo is generally better for transistor performance.

The key question this work is trying to answer – is one of these materials a better alternative to W for thin word lines. In this work the resistivity and transistor performance of W has not yet been measured under the same conditions and this is planned for future work.

I asked whether they had a sense of when W would have to be replaced in commercial devices and he said they did not, that ultimately the specific of individual products would determine this based not only on layer thickness but ultimately on what latency the overall device achieves, this may also be application dependent.

We also briefly discussed cost, my company IC Knowledge LLC is the world leader in cost modeling of semiconductors and MEMS, and I mentioned I thought Ru was too expensive for use in 3D NAND, he said he has colleges looking at this. I did some quick calculations using our Strategic Cost and Price Model and what I see is precursor costs of around $10 to $20 per wafer for W and Mo, and Ru is over an order of magnitude more expensive in my opinion making Ru too expensive to use.

In conclusion this work is an important step towards determining the suitability of Ru and Mo as long-term replacements for W to enable continued layer scaling and improved performance.

Also Read:

VLSI Technology Symposium – Imec Forksheet

VLSI Symposium – TSMC and Imec on Advanced Process and Devices Technology Toward 2nm

Is IBM’s 2nm Announcement Actually a 2nm Node?

July 18, 2021July 28, 2021

Wireless Transportation Disruption

Wireless Transportation Disruption
by Roger C. Lanctot on 07-18-2021 at 10:00 am
Categories: Automotive

One of the toughest tech tasks is adopting a new emerging technology that is fundamentally incompatible with the old. In the realm of connected cars, car makers and their suppliers labored for more than two decades on a wireless standard – called dedicated short-range communications (DSRC) – that was intended to enable intervehicle communications and communications between vehicles and infrastructure – V2X. The technology was expected to prevent collisions and allow for safer management of intersections with connected traffic lights – among other such scenarios.

With the reallocation of wireless spectrum by the Federal Communications Commission (FCC) late last year, the shift away from DSRC in favor of cellular-based V2X was complete. The resistance to this change remains however along with a near-pervasive denial across the wider ITS community encompassing both suppliers and their client DOTs.

This denial and resistance is sadly manifest in the recent statement from ITS America President and CEO, Shailen Bhatt. Regarding the FCC decision he says: “In light of the increase in fatalities on American roadways last year, the Federal Communications Commission (FCC) made a dangerous decision to give away a majority of the 5.9 GHz spectrum previously reserved for transportation safety. Not only has the FCC limited transportation use to 30 MHz of spectrum, it has failed to show that it will ensure that spectrum is usable by protecting it from harmful interference.”

He adds: “The only way to move from tens of thousands of deaths toward zero is by widely deploying V2X technology.”

In ITS America’s magazine he further notes: “ITS America has said repeatedly that V2X technologies are the best tool in our toolbox to dramatically reduce fatalities – they can prevent or mitigate up to 80% of non-impaired crashes, according to the National Highway Traffic Safety Administration (NHTSA).”

Putting money where its mouth is ITS America and the American Association of State Highway Transportation Officials (AASHTO) filed suit in District Court in Washington, DC, in June to enjoin the FCC, challenging its authority to reallocate the relevant wireless spectrum. This action is unlikely to succeed and sadly reflects the persistent myopia in the ITS community.

There is no question that V2X technologies – cellular-based or not – may be helpful in preventing crashes and saving lives, but that help will arrive only over a couple decades’ worth of deployment. Life saving solutions with more immediate impact are likely to emerge from regulatory efforts led by NHTSA, to advance the adoption of such technologies as lane keeping, blindspot detection, and intelligent speed assistance along with pedestrian detection and avoidance to mitigate the rise in pedestrian fatalities.

Bhatt’s position reflects the longstanding disconnect between the ITS community and the automotive industry. Because of a lack of a direct commercial connection between these two industries no common basis for engagement exists – in spite of there being board representation from auto makers at ITS America.

ITS America and its affiliates are disconnected from auto makers, wireless carriers, and technology companies such as Google, Amazon, and Microsoft. The onset of cellular-based V2X technology is something of a revelation as it provides – for the first time – a common communication protocol that car makers, semiconductor and technology companies, wireless carriers and the ITS community can all embrace.

While ITS America and AASHTO are suing to stop the FCC’s spectrum reallocation, ITS is simultaneously seeking reimbursement for DOT’s that have spent their own money on DSRC installations. One estimate from the USDOT puts the cost of decommissioning 67 existing operational DSRC installations and 65 sites currently in planning at $645M. Just as the ITS/AASHTO legal action is likely to fail, efforts to obtain funds for DSRC reimbursements will be unsuccessful.

Meanwhile, one stalwart ITS member, Applied Information, is offering to buyback DSRC equipment from DOTs. Says Applied Information’s President, Bryan Mulligan: “We were hoping, as were many others in our industry, that the FCC would preserve the full 75 megahertz for roadway safety. But now …we want to do our part to accelerate deployment of connected vehicle technology and its life-saving applications by providing roadway operators with a future-proof solution… Our buyback program enables DOTs to continue their DSRC connected vehicle programs with C-V2X seamlessly while helping to defray costs.”

There are indications that fellow ITS member suppliers Kapsch and Siemens are following suit with similar offers. All of this is to suggest that ITS America is not only out of touch with shifts in technology and the market, it is losing touch with its own members.

In the midst of this market muddle, I have to say that Bryan Mulligan at Applied Information emerges as a visionary leader in a hide-bound industry. Applied was first to step forward with the DSRC buyback offer and was also quick to bring dual mode modules to market to provide for a technology transition.

The automotive and ITS industries are caught on the horns of a dilemma. There is an apparent rise in highway fatalities afoot in the U.S. and answers are wanting. V2X technology will help, but coordinated action encompassing all relevant parties is required. What will not be helpful is an insistence on clinging to bygone technologies – like DSRC – that have been superseded by advances in sensor and cellular technologies. This is no time for lawsuits.

July 18, 2021August 22, 2024

GloFo inside Intel? Foundry Foothold and Fixerupper- Good Synergies

GloFo inside Intel? Foundry Foothold and Fixerupper- Good Synergies
by Robert Maire on 07-18-2021 at 6:00 am
Categories: Foundries, GlobalFoundries, Intel Foundry, Semiconductor Advisors, Semiconductor Services
2 Comments

Intel reportedly talking to Abu Dhabi to buy GloFo for $30B
Would jumpstart Intel Foundry but require investment & repair
Avoids IPO risk – Allows Abu Dhabi escape- NY benefits
Doesn’t impact near term shortage or market share

Reported by WSJ- Intel in talks to buy GloFo
The Wall Street Journal reported that Intel was in talks to buy Global Foundries for $30B. We have speculated n the past that this would be a good idea on a number of fronts. It would primarily give a second chance to Global Foundries effort at being a player in the foundry business which is widely seen by the industry as a lot less than a success. Abu Dhabi would get a clean, fast, easy exit and get most of its money back if not a tip. Intel would get someone already doing business as a foundry which is something it failed at.

To some extent two failures added together could be a success…

Nothing changes in the near term
This does nothing much to fix the near term chip shortages, nor would we see a real impact for quite some time. It does however accelerate Intel’s plans to be in the foundry business as GloFo obviously has a complete business structure in place that could be levered. This could cut years off of the effort needed by Intel and more importantly gives Intel a group that is more customer driven than its past foundry effort which failed in part due to its lack of understanding of how to service foundry customers.

Gives Intel a bigger Global footprint
Intel would obviously pick up Malta NY, Dresden Germany and Singapore. While none of the capacity is leading edge it does give Intel a good slug of middle of the road and trailing edge capacity which is where a lot of the current shortages are. Also important is that these locations are places where Intel currently has little to no presence. This means little to no duplication.

$30B would be an appropriate valuation
If we added up the costs of all the fabs Intel is getting, the new cost would likely be well in excess of $30B but in the condition they are today and as tailing edge capacity the value is clearly less. The real value is more in the fact that it is an operating foundry business that Intel does not need to build over a multi year period with a multi billion dollar investment. So in essence this is a time value of money especially given the near term value.

Intel will have to invest a lot of money to get the fabs running in a better manner. Abu Dhabi turned off the gusher flow of money and turned it down to a trickle of barely enough to keep the fabs running when it decided it wanted out of the failed investment. Intel would likely have to spend many times the paltry $1b/year scheduled for Malta.

Get GloFo back in the race or not? That is the question
Perhaps one of the more interesting questions is what Intel would do with GloFo, specifically Malta. Would they operate it as is as a middling factory of trailing edge or would they dump money into it to try and get it back into the Moore’s Law race. Would they essentially just use the GloFo foundry business infrastructure to give a leg up to leading edge fabs built in Arizona while keeping Malta to supply chips for dishwashers, toys and cars.

The answer is not clear. Malta may be too far gone and too old to get back in the race. It may be a lot easier to start with a clean slate in Arizona.

Malta does have a lot of the physical infrastructure needed but GloFo got rid of all the advanced people. There is infrastructure available to replace the two EUV tools that were sold off but its likely that it doesn’t have enough for a current start of the art fab.

Unless Intel can come up with a quick and relatively low cost upgrade it is likely that Malta will remain trailing edge.

Its also unclear if Intel would proceed with GloFo’s recently announced new $4B Asian fab. We would bet not as Intel likely needs to focus resources on Arizona.

Abu Dhabi gets a good exit
AbuDhabi has clearly wanted to exit this investment as it has been a lot less than successful. The most recent effort is a planned IPO. The risk we see is that while things look good right now due to the shortage in which you can charge any ridiculous price you want for chips, the longer term model of competing as a trailing edge fab against a tidal wave of cheap Chinese capacity is not quite that bright nor profitable.

So while it may be easy to sell off part of the $30B valuation to investors enthralled with the current chip shortage it may not be so easy for Abu Dhabi to get the rest of their money out a couple of years from now when the market gets back to its normal hyper competitive self.

If I were Abu Dhabi I would easily take a quick and clean exit now rather than taking risk for an upside down the road.

Dealing Direct
We find it interesting that the WSJ article suggested that Intel was dealing directly with Abu Dhabi, as management has clearly been focused on an IPO PR campaign for some time now complete with all sorts of high level support.

AMD not hurt
Some have noted that some of AMD’s chips are made by GloFo and there was a recent agreement for more. If AMD’s competitor owned GloFo that would complicate matters but we think it wouldn’t be all that bad as TSMC makes all of the bleeding edge MD parts while GloFo would only make the trailing edge parts which could easily be made elsewhere.

We also wonder if the AMD agreement was just more IPO window dressing

TSMC not impacted
The combination of Intel & GloFo would have little impact on TSMC. Intel will still be forced to give its advanced chip production to TSMC. TSMC’s better than 50% marketshare will not likely change at all.

When the shortage abates, TSMC could get more aggressive with trailing edge pricing and hurt Intel’s acquired GloFo capacity but we se little reason for them to do that as it would hurt their profitability as well.

Intel does get some new technology and markets
When GloFo announced its euphemistically called “pivot” away from the leading edge and the Moore’s law race it moved into some unique corners and hiding places in the industry that it could potentially dominate and hide from the mainstream CMOS technology capacity Tsunami coming from China.
SOI and communications became a focus as well as other specialty applications. We view this as a positive add for Intel as this could be parts of the market that it overlooked as not being big enough or not worthy of their time but are becoming more important.

We increasingly like Pat Gelsinger
It is clear that Pat Gelsinger is just what Intel needed. Big, bold, out of the box thinking for a company that got way too stodgy and complacent. He is taking on huge responsibility and risks but the reward is getting Intel back to leadership.

We wholeheartedly agree with the moves he is making. We would very easily trade a $9B memory fab for a $30B foundry every day. Intel is right to get out of memory and right to buy GloFo if it wants to be serious about being a foundry player

The Stocks
While we think that buying GloFo would be a super long term move the near term financials will get even uglier.

We had warned investors that Intel would have to “Triple Spend” ( 1-catch TSMC, 2-Build foundries 3-pay TSMC to build chips) Now if you add GloFo into the equation Intel will have to “Quadruple spend” by adding the costs to fix up and take on GloFo.

Intel is going to be hemorrhaging money at a geyser-like rate. Not to mention the $30B acquisition cost……

We see no real reason to own Intel in the near term and will have plenty of time to get into the stock as the positive results will take quite a lot of time.

GloFo’s margins will not be that great and will take down Intel’s margins a bit, especially when the shortage is over, so don’t look for this to be a hugely accretive transaction.

We highly endorse the move… Just not the stock right now….
We see little impact on other chipmakers and perhaps a small amount of positive for equipment makers stocks as it likely means incremental capital spending benefiting tool makers

Also Read:

Silicon Photonics Solutions Address Bandwidth, Reach, and Power Challenges

Enabling Silicon Technologies to Address Automotive Radar Trends and Requirements

Machine Learning Applied to Increase Fab Yield

Podcast EP29: An exploration of Minima’s energy optimized design technology

Podcast EP29: An exploration of Minima’s energy optimized design technology
by Daniel Nenni on 07-16-2021 at 10:00 am

Dan is joined by Lauri Koskinen, CTO and co-founder of Minima Technology. Dan explores the unique near-threshold design and operation of Minima’s energy optimized technology.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

July 16, 2021January 27, 2022

CEO Interview: Pete Rodriguez of Silicon Catalyst

CEO Interview: Pete Rodriguez of Silicon Catalyst
by Daniel Nenni on 07-16-2021 at 6:00 am
Categories: CEO Interviews, Semiconductor Services, Silicon Catalyst
1 Comment

Pete Rodriguez has over 35 years of experience in the Semiconductor industry. Pete is currently CEO of Silicon Catalyst and on the board of Hysai, advisory board of Harvest Management Partners and an observer on the boards of Mentium Technologies, Espre Technologies and Owl AI. Pete was formerly VP & GM of Interface and Power at NXP Semiconductors. Prior to NXP Pete was CEO of Exar Corporation, CEO of Xpedion Design Systems, Chief Marketing Officer at Virage Logic, Major Account Manager at LSI Logic and Program Manager at Aerojet Electronic Systems. He spent twelve years as an entrepreneur with three different startups and has raised over $30 Million in venture capital.

He retired from the US Naval Reserves with the rank of Commander. Pete has served on public, private, advisory and non-profit boards of directors. He is a graduate in strategy and policy of the Naval War College. Pete has an MBA from Pepperdine University, an MSEE from Cal Poly Pomona, and a BS in Chemical Engineering from the California Institute of Technology.

What’s the backstory about Silicon Catalyst; why did you join?

Rick Lazansky, Chairman and co-founder shared his ideas to help out hardware startups a decade ago, I met with him and Mike Noonen in 2014 as they were getting started and I attended the 2015 launch at Avaya.

Later I left NXP in early 2016 and retired after successfully growing and running interface and power, one of the very best businesses in the company. Rick approached me to become CEO and I joined late in 2017, excited about helping semi startups, growing the ecosystem and taking SiC to the next level.

What are SC’s goals?

To really, really help a growing number of semi startups worldwide. To continue to grow the breadth and depth of the ecosystem in order to be able to deliver more in every way to each startup.

To eventually make a little $ as portfolio companies successfully exit. It has been a labor of love with well over a total of 50 Silicon Valley-executive man-years of sweat equity and a ton of charity from our partners.

What are you seeing with respect to technology trends, application areas, technical innovations, etc.?

We see companies across the board, from AI to Lidar to mmWave to 5G to security to sensing. As Moore’s law slows/ends we are seeing more innovation/creativity in solving problems, not just driving for the latest tech node. We are also seeing many unique sensing solutions leveraging new capabilities in MEMS, CMOS + and sensing.

Why expand to the UK?

We started in Silicon Valley, then we launched a JV in Chengdu focused on power, we had good discussions with the EU about setting up an incubator in Europe and had strong strategic partners SOITEC, Bosch and ST Micro (our 2nd strategic and IKP) as well as good European operations by our closest IKPs (up to 48 now) TSMC and Synopsys. Then COVID hit and delayed the EU entry significantly. In parallel ARM became our first strategic and IKP, this combined with the UK govt.’s increased focus on semis post Brexit, several new UK based IKPs (4), UK based startups joining the portfolio (2), UK based advisors and the availability of two world-class managing partners (Ron and Sean) sealed the deal

Further expansion in other regions of the world?

We are still looking at the rest of the EU, though some things are segmenting by countries vs. a single EC. We just admitted our first Indian based company (AlphaICs) and have several great advisors in India. In addition, we are partnering with other incubators/ accelerators (at no extra cost to the startup) around the world at least a half dozen and now have official partnerships with two leading incubators/accelerators Venture Lab in Canada and Octane in Southern CA. In these partnerships these incubators will receive financial benefit for their minority groups of semi companies and the companies will receive all of Silicon Catalyst’s benefits, as well as the extended benefit of two slightly overlapping ecosystems (advisors, investors, strategics, etc.). We are also partnering with University incubators like Cornell (see the Semiwiki coverage) as an extension of our University and Incubator partnership programs.

Suggestions for semi industry entrepreneurs ?

We are here to help and advise, we will spend quality time with you and your team, and provide great advice and help even if you decide not to join. We focus on all of the areas that a leading VC does but we add the personal touch of an experienced partner as your advocate and world class experts from our >200 advisor network and the key technologists from our strategic partners and IKPs…Each of our portfolio company’s incubation is custom tailored for a minimum of 2 years – not the usual 3 month cohort duration in other incubators.

Further information about our organization is generally available from our website, as well as details from the recent coverage of the launch of our UK operation. Check it out at www.siliconcatalyst.uk and on SemiWiki: https://semiwiki.com/events/299740-silicon-catalyst-is-bringing-its-unique-startup-platform-to-the-uk/

Also Read:

CEO Interview: Sivakumar P R of Maven Silicon

Ten Lessons Learned from Andy Grove

CEO Interview: Deepak Shankar of Mirabilis Design

July 15, 2021April 15, 2022

Cadence Tensilica FloatingPoint DSPs

Cadence Tensilica FloatingPoint DSPs
by Kalar Rajendiran on 07-15-2021 at 10:00 am
Categories: Cadence, IP

Being engrossed in the digital information world, it is easy to forget that the real world is comprised of mostly analog signals and data. Digital Signal Processors (DSP) take digitized forms of these worldly signals and manipulate them mathematically. Although floating-point is a more relevant and accurate way of representing real world data, a significant volume of DSPs in deployment are fixed point DSPs. And these fixed-point DSPs have been meeting the needs of commercial applications well. Traditionally, floating-point computations have primarily been used in scientific applications.

Historically, the term floating-point has only received mainstream attention when bugs or errors have caused critical floating-point calculations to be performed incorrectly. Floating-point remained a topic of interest for only certain specialized applications until recently. It is not surprising that there are not many DSP cores optimized for floating point computations. Commercial, consumer and industrial market requirements are changing. As highlighted during executive keynotes at the CadenceLIVE Americas 2021 conference, today’s common applications are as complicated and demanding as “rocket science” applications. Floating-point DSPs have become imperative for today’s market needs. It is in this context that Cadence’s recent unveiling of their Tensilica FloatingPoint DSP family of products takes significance.

I had an opportunity to talk with Ted Chua, director of product marketing and management of Tensilica DSPs at Cadence. The following is a synthesis of what I gathered from our conversation.

Markets and Requirements

Applications that could benefit from floating-point DSPs range from energy-efficient solutions for battery-operated devices to artificial intelligence/machine learning (AI/ML), motor control, sensor fusion, object tracking and augmented reality/virtual reality (AR/VR) applications in the mobile, automotive, hyperscale computing and consumer markets. Many of these applications are fast evolving and moving from the cloud to the edge. What is needed is a family of floating-point DSP cores to address different market needs for quick time to market. The family must be designed for scalability with applications and supported with ease of configurability. The cores should allow for custom instructions for adapting to market trends. And these cores must be optimized for power, performance and silicon area to keep product costs competitive.

Cadence Tensilica FloatingPoint DSP Solutions

In general availability now, the family of products announced last month includes the Tensilica FloatingPoint KP1, KP6, KQ7 and KQ8 DSP cores. The products are built off of the widely used and well established Xtensa platform and ecosystem and support the Xtensa LX Secure Mode. The secure mode is a unique feature in a DSP core and enables customers to partition the memory into secure and non-secure regions and allow the protection of secure memory from untrusted third-party code. This feature permits inclusiveness of a broader selection of third-party codes without compromising on system security.

Refer to the figure below for some key features.

Scalable, Configurable and Extensible

Scalability– The DSP cores range from the ultra-low energy and very small 128-bit FloatingPoint KP1 DSP core to the super-high performance 1024-bit FloatingPoint KQ8 DSP core and are well-suited for a broad array of applications. Customers have the flexibility to choose the optimal cores for their respective application needs. Support for IEEE754 half-precision, single-precision and double-precision floating point is unique in the specialized floating-point DSP market today and further enhances the scalability of Cadence’s offering.

Configurability– The development platform makes it easy to configure to different SIMD widths by automatically selecting the vector packages without unnecessary hardware.

Extensibility– The Verilog-like Tensilica Instruction Extension (TIE) language allows customers to easily design and add custom instructions and custom interfaces to the DSP. It enables them to further enhance the performance and bring highly differentiated products to their customers.

Performance, Power and Area (PPA)

The new DSP cores deliver a 25% performance improvement in fused multiply-add (FMA) operations compared to Tensilica’s fixed-point DSPs with vector floating point unit (VFPU) add-on. The TIE language not only allows for product differentiation but also enables further enhancement of performance of the product. The new DSP cores offer up to 40% silicon area savings compared to similar class of fixed-point DSPs with VFPU add-ons. Customers have the option to choose the optimal DSP core that fits their PPA budget for their application.

Overall, the optimized PPA benefits of the Tensilica FloatingPoint DSP family is a key value proposition for customers to bring differentiation to their respective customers. Refer to the figure below.

Ease of Development

Ease of development is as important an aspect as the product features when it comes to bringing a solution to market ahead of competition. The development platform and productivity tools suite play a very important role in this aspect. Tensilica FloatingPoint DSPs are delivered with a complete set of software tools. This comprehensive toolset includes the linker, assembler, debugger, profiler, and graphical visualization. Refer to the figure below for more details. When working with large systems or lengthy test vectors, the Tensilica TurboXim™ simulator option achieves speeds that are 40X to 80X faster than the ISS.

The Tensilica FloatingPoint DSPs support all major back-end EDA flows. The optimized Eigen, NatureDSP, simultaneous localization and mapping (SLAM) and math software libraries enable easier migration of customers’ software to fully leverage the FloatingPoint DSPs.

Summary

The Tensilica FloatingPoint DSP Cores address the higher-precision data representation-format need as well as the scalability, configurability, extensibility and PPA requirements of modern commercial, consumer and industrial applications. The press announcement can be found here and more details can be accessed here at the Product section of Cadence website. If you are developing products for any of these (refer to the above figure) high-growth, fast changing markets, you may want to explore ways to benefit from Cadence’s recently introduced Tensilica FloatingPoint DSP cores.

Also Read:

Features of Short-Reach Interface IP Design

112G/56G SerDes – Select the Right PAM4 SerDes for Your Application

Lip-Bu Hyperscaler Cast Kicks off CadenceLIVE

July 15, 2021February 2, 2022

Is EDA Growth Unstoppable?

Is EDA Growth Unstoppable?
by Mike Gianfagna on 07-15-2021 at 6:00 am
Categories: ESD Alliance, Semiconductor Services, Wally Rhines
2 Comments

SemiWiki has covered the Q2, Q3 and Q4 ESD Alliance quarterly revenue reports previously. The Q2 2020 report suggested that EDA had COVID immunity. The Q3 2020 report inspired an Up and to the Right comment. The Q4 2020 report demanded a Juggernaut label. And now the Q1 2021 report posts yet more record-breaking growth. This is indeed very happy news. I’ll share the details in a moment. As I dug into all the good news, I couldn’t help but wonder, “when will this end” or perhaps “will it ever end?” I had the opportunity to explore these questions with Dr. Walden Rhines, the executive sponsor for the SEMI Electronic Design Market Data report. Is EDA growth unstoppable? As it turns out, maybe yes, maybe no. Makimoto’s Wave is part of the discussion, as is the changing landscape in China. More on that in a moment.

First, the good news. Electronic System Design (ESD) industry revenue increased 17% to $3,1571.7 million in Q1 2021 – the strongest first-quarter growth ever recorded. The four-quarter moving average, which compares the most recent four quarters to the prior four, rose 15%, the highest annual growth since 2011. The companies tracked in the report employed 49,024 people in Q1 2021, a 6.7% increase over the Q1 2020 headcount of 45,938 and up 1.1% compared to Q4 2020. I looked hard for some bad news but found none. Wally summed it up by saying, “All product categories significantly contributed, with double-digit growth in the CAE, IC physical design and verification, PCB, MCM, and semiconductor IP segments.”

With that discussion out of the way, I dug a bit deeper with Wally regarding the story behind the numbers. We discussed many data points and trends. What stood out for me were two. One suggests that EDA growth indeed may be unstoppable for the foreseeable future and another that suggests there is a potential impact brewing that could slow things down. Let’s look at both.

Makimoto’s Wave

Wally has referred to this phenomenon many times in the past. The concept was first presented in 1991 by Dr. Tsugio Makimoto, the former CEO of Hitachi Semiconductors and former CTO of Sony. The model describes how the semiconductor market swings between specialization and standardization on roughly a ten-year cycle. The forces at play here can be summarized as follows:

When there is widespread standardization (same hardware):

There arises a need for more differentiation
There arises an expectation of value differentiation

These forces move the market toward customized hardware to address the shortcomings, and so we see a lot of different hardware. At some point, all this custom hardware creates another set of requirements:

The need for better operational efficiency
The need to lower cost
The need to improve time to market (custom hardware takes time to build)

And so, the cycle continues. Recent data suggests we should now be moving to an era of standardization. The observed facts are quite different, however. Custom hardware to fuel things like artificial intelligence and machine learning are very, very widespread. What does this mean for the future of semiconductors and EDA?

There is no way to conclusively predict the future but let me offer my point of view. The move from custom hardware to standard hardware is often catalyzed by stability in the software. In this case, custom hardware results in small incremental improvements and so standard hardware takes hold and software innovation leads the way. The question to ask is when will AI/ML software become stable, such that custom hardware no longer has a big impact? I would argue that event is over ten years away, maybe longer. We should remain in an era of custom hardware for some time. EDA growth could indeed be unstoppable.

The China Syndrome

No, not the famous movie from 1979. I got some very interesting data from my conversation with Wally that doesn’t appear in the press release. China’s consumption of EDA tools is huge and growing very, very rapidly. Q1 2020 vs. Q1 2021 growth is an astounding 99.3%. If you add IP consumption to the mix, year-over-year growth becomes 72%. Compare these growth numbers to other regions and they are a minimum of 2X larger, typically over 4X larger. Note the baseline these numbers are growing from is big. Similar in size to the largest reporting regions in the press release.

With these facts on the table, let’s add two more relevant bits of information:

1) China has a strong appetite to be self-sufficient. There are major investments underway in design and manufacturing infrastructure. Wally also shared that the total revenue for fabless chip companies in China was $58.5B in 2020. There is an ecosystem available there.

2) Almost no Chinese EDA or IP companies report for the SEMI Electronic Design Market Data report.

So what happens to all that EDA revenue if it begins to be sourced domestically in China? Will it disappear from the SEMI Electronic Design Market Data report? Perhaps. EDA revenue growth may be slowing down a lot in the not-to-distant future in this case.

You Decide

So, there are two points of view to consider. Is EDA growth unstoppable? You decide.

Also read:

The Juggernaut Continues as ESD Alliance Reports Record Revenue Growth for Q4 2020

ESD Alliance Report for Q3 2020 Presents an Upbeat Snapshot That is Up and to the Right

EDA Appears to Have COVID Immunity – ESD Alliance Reports Strong Q2 2020

July 14, 2021March 24, 2022

Fully Modeling the Semiconductor Manufacturing Process

Fully Modeling the Semiconductor Manufacturing Process
by Tom Simon on 07-14-2021 at 10:00 am
Categories: Dassault Systemes, EDA

A lot of folks in the semiconductor business are familiar with Dassault Systèmes because of their product life cycle management (PLM) products for IC design. They are, of course well known in other industries as well for their 3D modeling and simulation software. Over the years they have added capabilities and intelligence to their product offerings, allowing them to be used for ever more sophisticated and comprehensive modeling and simulation. Decades ago, they worked with Boeing to create a complete 3D model of the 777 aircraft during its development and today their customers can also model the production planning and operations of their products across many industries including semi fabs.

In a recent conversation with Dassault Systèmes’ Simon Mellier I learned a lot about their new vision for improving semiconductor manufacturing. Dassault Systèmes has expanded the concept of 3DEXPERIENCE to address manufacturing challenges in a new way. This new concept is called 3DEXPERIENCE Virtual Twin. Much as it sounds, it leverages an executable model of every element in a fab. Simon emphasized that this is of particular interest for the semiconductor industry due to the huge complexity of its products and production models.

Having a complete and fully functional model of a fabrication facility offers numerous benefits. In our discussion Simon touched on a number of these. A fully instantiated virtual twin doesn’t only model the operation of each piece of equipment, it can also help foundries extend to the facility operations including all workflows.

One example he used was in the case of maintenance. Not only can the virtual twin help provide feedback and information about potential equipment failures, it can also offer a laboratory for training technicians on performing complex maintenance operations. Technicians can practice the steps for equipment repairs or maintenance prior to bringing a high value fab line down to perform the actual repairs. As a result, such operations are likely to be more efficient, leading to reduced equipment down time.

Modeling the Semiconductor Manufacturing Process

With a virtual twin, manufacturing processes and parameters can be optimized to improve yield and efficiency. The virtual twin can be kept up to date with real performance metrics from the physical fab, providing a closed loop to ensure high accuracy. Of course, this is not all peaches and cream. For this technique to work, detailed information about the foundry equipment is necessary. Ideally the manufacturers will provide intelligent 3D models and information about external interfaces so that a high accuracy model of every aspect of the foundry can be captured. So naturally, sophisticated security mechanisms are required to secure intellectual property. The benefits of a highly integrated executable virtual twin clearly exceed the effort to get and organize the information needed to build the models. There are some parallels with the methods that are used in IC design for dealing with IP blocks.

Dassault Systèmes has a bold vision for virtual twins in semiconductor manufacturing. They have been applying these same techniques at growing scale in other industries. The advantages in planning and operation are pretty much self-apparent. There are a lot of pieces of this that can be fleshed out. Expect to see more articles here on the specifics. In the meantime, it is worthwhile to check out the Dassault Systèmes website for more information on virtual twins and how they represent the next stage in improving manufacturing efficiency.

Also Read

Optimizing high performance packages calls for multidisciplinary 3D modeling

A Brief History of IP Management

Delivering Innovation for Regulated Markets

July 14, 2021May 6, 2022

Get a Jump-Start on Your Next IoT Design with Sondrel’s SFA 100

Get a Jump-Start on Your Next IoT Design with Sondrel’s SFA 100
by Mike Gianfagna on 07-14-2021 at 6:00 am
Categories: Aion Silicon, Semiconductor Services

The concept of platform-based design has been around a long time. I can recall Nokia’s early cell phone products used the strategy very effectively. They were able to turn out new phones quickly by leveraging their existing chip design as a baseline on which to add features. This is commonplace today but was innovative at that time. Fast-forward to the present time and the requirements are quite similar – get the next product to market as quickly as possible by leveraging reuse wherever possible. A contemporary delivery vehicle for this strategy is called a reference design. Let’s explore one from Sondrel to see how it helps to get a jump-start on your next IoT design.

Sondrel is known for being specialists in complex digital ASICs. You can learn more about Sondrel from this interview with their CEO, Graham Curren. The company offers a series of reference designs for several major application areas. You can learn about the Architecting the Future™ family here. Let’s examine the SFA 100 and its applications for intelligence gathering at the edge.

The SFA 100 IP reference platform is intended to make high-performance, battery powered IoT devices easy and fast. As Graham Curren explains, “Knowledge is power but raw data needs to be processed to make it useful.” SFA 100 addresses this challenge head-on by providing a compact and powerful compute capability to intelligently transform data into knowledge to fulfill the “smart” requirement for IoT at the edge. Thanks to the platform approach, most of the design work has already been done. The user provides their own unique IP and Sondrel incorporates that with some minor tweaks to create the final ASIC. The result is reduced risk, design costs and time-to-market. Graham claims by up to 30% when compared to starting from scratch.

Inside SFA 100

The design has an Arm® CPU to locally process data gathered from sensors for transmission via wired or wireless protocols to facilitate further analysis. Security is built in using standard secure/encrypted protocols.

The SFA 100 facilitates integration of a machine-learning engine with a low cost, low power edge device. More details of the architecture include an Arm® Corstone™-300 subsystem for security. The subsystem contains an Arm Cortex®-M55 with secure boot with cryptographic algorithm accelerators and support for TrustZone® and CryptoCell™ for additional security for the transmitted data. Also included is the Arm Ethos™-U55 Machine Learning (ML) processor that provides a 480x increase in ML performance.

GPIO, I2C, UART and QSPI peripheral interfaces are on-board to capture sensor data, such as video, image, and sound along with a 12-bit audio DAC for voice commands. The design can operate on battery power, which is complemented by low power, wireless connectivity using either Bluetooth BT5.1-LE or ZigBee. With this platform, design teams can create an endpoint device to perform a variety of smart processing, such as voice activation, image classification, gesture recognition, filtering, inference, and tracking depending on the application. If more memory is needed, it can easily be added via the DRAM interface.

In short, designers get a serious jump-start with SFA 100. To further reduce risk, Sondrel also offers full turnkey design services to deliver fully tested, production silicon. A high-level block diagram of the SFA 100 is shown below.

SFA 100 block diagram

You can read the press release announcing the SFA 100 here, and you can download the data sheet here. Now you know how Sondrel helps to get a jump-start on your next IoT design.

Also Read:

Webinar: Challenges in creating large High Performance Compute SoCs in advanced geometries

Sondrel Explains One of the Secrets of Its Success – NoC Design

CEO interview: Graham Curren of Sondrel