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VLSI Technology Symposium – Imec Forksheet

VLSI Technology Symposium – Imec Forksheet
by Scotten Jones on 07-06-2021 at 6:00 am

FinFETs devices are reaching their limits for scaling. Horizontal Nanosheets (HNS) are a type of Gate All Around (GAA) device that offers better scaling and performance per unit area. HNS is the logical next step from FinFETs because HNS processing is similar to FinFETs with a limited number of process changes required.

At the VLSI Technology Symposium, Imec presented on their Forksheet (FS) work that offers enhanced HNS scaling and performance. I had an opportunity to discuss the work with Naoto Horiguchi of Imec.

Authors note, The height of standard cells used to create logic layouts is determined by the metal pitch and number of tracks high the cell is.

Cell Height = Metal Pitch x Tracks

If you look at a 5-track HNS cell a significant amount of the height is taken up with the n to p device spacing, see figure 1. left side. In a FS process a dielectric wall is introduced between the n and p devices enabling reduced n to p spacing, see figure 1. right side (for example ~40nm to ~17nm).

VLSI2021 T2 1 Mertens v2 Page 05

Figure 1. HNS Versus FS Structure.

The reduced n-p spacing can be utilized in two different ways. The first option is to utilize the additional space in the cell to make the sheets wider improving drive current. The dielectric wall introduced for FS also reduces capacitance. Figure 2. Illustrates the layout and performance advantages.

VLSI2021 T2 1 Mertens v2 Page 07

Figure 2. Power – Performance – Area (PPA) Advantage.

The second option is to keep the sheet width the same and reduce the tracks. FS can enable a 4.3-track cell and even 4-track cells are possible with a special Middle-Of-Line (MOL) construct.

FS do degrade the electrostatic control of the device slightly versus the GAA structure of a HNS, FS can be thought of as a FinFET turned on its side with gates on three sides as opposed to GAA structures. Authors Note, FinFET gate length (Lg) is generally limited to ~16nm due to leakage issues whereas HNS Lg can scale to ~13nm. In this work HNS and FS were created on the same wafer and the SSSAT (Subthreshold Slope) and DIBL (Drain Induced Barrier Lowering) were identical, but the Lg was a relatively long 22nm

TCAD work is underway to evaluate shorter Lg. Figure 3. illustrates the SS degradation for a 16nm Lg and shows how the degradation can be mitigated by recessing the channel.

VLSI2021 T2 1 Mertens v2 Page 28

Figure 3. FS Electrostatic Degradation.

In addition to enabling improved scaling and performance, FS have two other advantages over HNS.

When creating multiple threshold voltages, multiple types, and thicknesses of work function metals (WFM) are deposited and patterned. The high aspect ratio of the HNS devices can result in wet etch undercut of the WFM. The introduction of the dielectric wall provides a WFM etch barrier preventing undercut, see figure 4.

VLSI2021 T2 1 Mertens v2 Page 09 fs hns

Figure 4. FS Dielectric Barrier.

Another advantage of the FS is the dielectric wall provides additional mechanical support to the channel nanosheets. I asked about drying concerns with HNS structure and was told that with the FS support longer channels were still mechanically stable and current hot IPA drying techniques were sufficient.

Of course, an obvious question is how complex it is to implement FS in a HNS process and the answer is it is very simple. You simply must deposit a conformal dielectric layer, in this case Silicon Nitride (SIN) and then etch the film back. Wherever the devices are closely spaced the SiN dielectric wall is left in place. Figure 5 illustrates the dielectric wall process.

VLSI2021 T2 1 Mertens v2 Page 14 hns vlsi

Figure 5. Dielectric Wall Formation.

In conclusion the FS is a promising extension to HNS offering improved scaling and performance with minimal additional process complexity.

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