This is another installment covering TSMC’s very popular Open Innovation Platform event (OIP), held on August 25. This event presents a diverse and high-impact series of presentations describing how TSMC’s vast ecosystem collaborates with each other and with TSMC. Not all SerDes are the same. The presentation covered here, from Cadence, discusses the various flavors of LR, MR/VSR and XSR high speed SerDes and where they fit best. When it comes to 112G/56G SerDes, you really need to select the right PAM4 SerDes for your application.
The presentation was given by Wendy Wu, product marketing director at Cadence. Wendy has also worked in marketing and applications engineering at NetLogic Microsystems, Broadcom and Cavium. Wendy speaks with strong authority on the topic. She began her talk discussing a semiconductor law that is somewhat less know than Moore’s Law, but very relevant. Rent’s rule is based on internal memoranda at IBM from 1960. It basically says that the number of I/O pins tracks the number of gates/transistors. So, functionality increase requires I/O bandwidth to increase. This is why the topic is inherently important.
Wendy then discussed how high-speed interconnect is the backbone of cloud data centers. Higher throughput with lower latency and flat power describe the challenge. Wendy shared an interesting statistic – 85% of the traffic in a typical data center is between compute nodes in that data center. Data communications is clearly a key item for continued growth in this huge market.
Looking at AI requirements for high-speed comms, 7nm and 5nm are the preferred nodes today, with 3nm around the corner. We are at the cutting edge here. Wendy then discussed the various applications for 56G and 112G SerDes. She touched on four areas:
Long reach: backplane applications – between processors and racks. Drive, performance and signal loss are key parameters here.
Medium reach: chip-to-chip and mid-range backplanes.
Very short reach: chip to module applications.
Extra short reach: die-to-die, system in package applications.
With regard to die-to-die communications, three methods were discussed. This technology is also an enabler for the growing chiplet market. There is the previously discussed PAM4 SerDes approach. NRZ serial interface is another approach. Finally, a parallel interface can be considered, similar to what is used for HBM stacks with a silicon interposer. Each of these approaches has its strengths and weaknesses.
Next, Wendy examined analog vs. digital equalizer architectures. An analog solution delivers better density and lower power but is susceptible to channel noise and can equalize up to 20db of loss. Analog-to-digital, DSP-based approaches are more stable and reliable. They can equalize up to 40db of loss. Traditionally, these solutions have been higher power than analog. Starting at 7nm and below, the power requirements of digital solutions are very similar to analog. With all this background, what is the best approach? Clearly that depends on the application. Wendy provided a good overview of where each technology fits. This is captured in the diagram below.
Wendy then discussed the 56G and 112G offerings from Cadence, built by a best-in-class engineering team that is strong in both analog and digital techniques. The IP is fully compliant with relevant industry standards. She also pointed out that Cadence works with connector, cable and optical module suppliers to ensure good interoperability. Both 56G and 112G parts are proven with multiple test chips. She explained that the portfolio can support requirements from LR to XSR. These points are illustrated by the graphic at the top of this post.
Wendy went into some detail on the Cadence 112G-LR DSP SerDes. The key advantages are summarized in the figure below.
Wendy concluded with a discussion of the Cadence UltraLink D2D PHY IP. This IP can connect two designs through a multi-chip module or an organic substrate. The figure, below, summarizes the performance parameters of this IP.
You can learn more about how to select the right PAM4 SerDes for your application and the Cadence IP portfolio here.