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Semiconductor Expert Forum

Podcast EP191: The Impact of Evolving AI System Architectures and Samtec’s Role with Matt Burns

Podcast EP191: The Impact of Evolving AI System Architectures and Samtec’s Role with Matt Burns
by Daniel Nenni on 11-03-2023 at 10:00 am

Dan is joined by Matthew Burns, Matt develops go-to-market strategies for Samtec’s Silicon to Silicon solutions. Over the course of 20+ years, he has been a leader in design, technical sales and marketing in the telecommunications, medical and electronic components industries.

Matt and Dan discuss revelations from the recent AI Hardware & Edge Summit and the OCP Global Summit. The deployment of new AI system architectures are enabling many new capabilities, including those based on large language models (LLMs).

These architectures demand tremendous data communication performance, an area where Samtec can make a huge difference. In this broad and informative discussion Matt describes how Samtec’s products can help to deploy new AI system architectures, with a look at what the future holds.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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Executive Interview: Tony Casassa, General Manager of METTLER TOLEDO THORNTON

Executive Interview: Tony Casassa, General Manager of METTLER TOLEDO THORNTON
by Daniel Nenni on 11-03-2023 at 6:00 am
Categories: CEO Interviews, Mettler-Toledo, Semiconductor Services

TC MT Thornton

Tony Casassa has served as the General Manager of METTLER TOLEDO THORNTON since 2015, after having joined the company in 2007 to lead the US Process Analytics business. Prior to spending the last 16 years with METTLER TOLEDO, Tony held various business leadership positions for 2 decades with Rohm and Haas Chemical. A common thread throughout his 35+ year career has been bringing new innovations to market that delivers enhanced process control and automation for the Semiconductor and Life Science industries.

Tell us about Mettler Toledo Thornton?

METTLER TOLEDO THORNTON takes important or critical Pure water process measurements that are currently OFFLINE, and brings them online in a real-time, continuous measurement approach.  Measuring in-situ on a real-time and continuous basis eliminates sampling errors/contamination risks and provides increased process transparency.

Our focus is on segments that use pure water for critical process stages and where water quality has high value and process impact.  Our customers benefit from the deep segment competency & process expertise that our experts have developed over decades in the industry.

What application areas are your strongest?

Mettler Toledo Thornton is the global leader in the measurement and control of the production and monitoring of Pure and Ultrapure water (UPW) for the Semiconductor (Microelectronics) industry.  We provide a full portfolio of the process analytics that are required for the real time monitoring of these critical waters in the UPW loop, distribution system or reclaim.

What problems are you solving in semiconductor?

The semiconductor industry is constantly developing new ICs that are faster, more efficient and have increased processing capability. To accomplish these advances, the architecture and line width on the ICs has become narrower and narrower, now approaching 2 to 3 nanometers.  To produce these state-of-the-art ICs, the SEMI Fab requires vast quantities of Ultrapure water that is virtually free of any ionic or organic impurities.  Mettler Toledo Thornton R&D has developed, and we have introduced to the market the UPW UniCond® resistivity sensor that exceeds the measurement accuracy of previous or current resistivity sensors on the market.  This sensor exceeds the stringent recommended measurement limits published by the SEMI Liquid Chemicals committee.  Measurement and control of ionic impurities in Ultrapure water is critical but so is the measurement and control of organics. Our online Low PPB 6000TOCi provides the semiconductor industry a TOC instrument that accurately measures in the sub ppb TOC range but also uses 80% less water than other instruments.  The control of dissolved oxygen and silica are critical measurements for the SEMI Fab and our analytics provide industry setting accuracy with longer service life and reduced maintenance.

Another key priority for the industry is sustainability and the need to reclaim water & reduce overall water consumption.   To minimize adverse impact on wafer yield,  it is imperative to fully understand the water quality & risk of contaminants to enable informed decision making on where & how the various reclaimed water streams can be recycled or reused.  Mettler Toledo Thornton’s continuous, real-time measurements enable fast, confident decisions in the water reclaim area.

This full range of process analytics helps the SEMI industry monitor and control the most critical solvent for wafer quality, increased yield and reduced defects while obtaining sustainability goals.

How are your customers using your products?

For the semiconductor facility the production of Ultrapure water is the first step in the SEMI water cycle, but the UPW is the universal solvent used in the Tools for cleaning the wafers after photolithography, epitaxy, RCA process and other processing steps.  Our instruments are critical in the monitoring of the Tools process and assure the cleaning of the wafers.  The next step in the water cycle for the UPW is in the Reclaim/Reuse/Recycle, where the SEMI Fab utilizes Mettler Toledo Thornton process analytics to decide if the UPW can be brought back to the UPW purification process to reduce water discharge and improve industry sustainability.

What does the competitive landscape look like and how do you differentiate?

The current super cycle in the semiconductor industry has resulted in numerous companies pursuing opportunities for their products in this space.  Some are historical suppliers while there are new competitors in the market.  Mettler Toledo Thornton has been involved in the semiconductor industry for over 40 years and active in working with the industry to establish the accuracy and technical specifications for UPW.  The research work at Mettler Toledo Thornton conducted by that Dr. Thornton, Dr. Light and Dr. Morash established the actual resistivity value of Ultrapure water which  is the current standard for the industry.  We have been a partner with all the leading global semiconductor companies to develop the most accurate online analytical instruments.  Our focus on continuous, real-time measurements provides our customers with the highest level of process transparency relative to other batch analyzers or offline measurements.

A key factor in the establishment of Mettler Toledo Thornton as a global leader in the semiconductor industry has been our active participation and membership of the SEMI committees that are establishing the recommended limits for the SEMI industry.  Our global presence and service organization provides the semiconductor facility with the ability to standardize on an analytical parameter and employ it across all their facilities and locations.

What new features/technology are you working on?

Our focus is responding to the needs of the market as they strive to improve yield, minimize water consumption, increase throughput and reduce costs.  We have recently brought a rapid, online microbial detection to market that replaces the need for slow, costly and error-prone offline test methods.  Our new Low PPB TOC continuous online sensor reduces water consumption by 80% vs other company’s batch instruments.  Our latest innovation is the UPW UniCOND sensor that delivers the highest accuracy on the market today.  We continue to develop new technologies that enables the industry to achieve sustainability goals without sacrificing wafer yield.

How do customers normally engage with your company?

Mettler Toledo Thornton has a global presence with our own sales, marketing, and service organizations in all the countries with semiconductor facilities and Tool manufacturers.  The local sales and service teams have been trained on the complete water cycle for semiconductor which gives them the expertise to engage with the semiconductor engineers to provide the technical solutions for UPW monitoring and control.  We conduct numerous global webinars and in-person seminars to provide the semiconductor industry the opportunity to learn about the most recent advances in analytical measurements.  These seminars also provide the local semiconductor facilities the opportunity to be updated on the most recent UPW recommended limits because of our participation in the technical committees.  With our industry specialists we produce and publish numerous White Papers and Technical documents that give the industry the opportunity to gain further insight into the latest advancements.

Also Read:

A New Ultra-Stable Resistivity Monitor for Ultra-Pure Water

Water Sustainability in Semiconductor Manufacturing: Challenges and Solutions

CEO Interview: Stephen Rothrock of ATREG

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Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points

Webinar: Fast and Accurate High-Sigma Analysis with Worst-Case Points
by Daniel Payne on 11-02-2023 at 10:00 am
Categories: EDA, Events, MunEDA

Worst case point min

IC designers are tasked with meeting specifications like robustness in SRAM bit cells where the probability of a violation are lower than 1 part-per-billion (1 ppb). Another example of robustness is a Flip-Flop register that must have a probability of specification violation lower than 1 part-per-million (1 ppm). Using Monte Carlo simulation at the SPICE level for normal distributed performance with a small sample size to achieve 1 ppm requires 4.75 sigma analysis, while reaching 1 ppb increases to 6.0 sigma analysis. The problem is that for non-normal distributed performance the standard Monte Carlo approach requires a sample size that is simply too large to simulate, so a more efficient approach is required and that’s where high-sigma analysis and worst-case points come into use.

Register for this MunEDA webinar scheduled for November 14th at 9AM PST, and be prepared to have your questions answered by the experts.

MunEDA is an EDA vendor with much experience is this area of high-sigma analysis methods, and they will be presenting a webinar on this topic in November. I’ll describe some of the benefits of attending this webinar for engineers that need to design for robustness.

In the non-normal distribution case to prove that the failure rate is below a required limit of 1 ppm, or 4.75 sigma, requires 3 million simulations. To estimate the failure rate to a 95% accuracy as being between 0.5 ppm and 1.5 ppm requires a much larger 15.4 million simulations. Trying to achieve 6.0 sigma with this same math then requires billions of simulations, something impractical to even consider.

The webinar goes into details on how parameter variation and yield are impacted by Monte Carlo techniques like brute-force random sampling versus searching the failure region by an optimizer to find the highest density of failing points. The worst-case point is the region which has the highest density of failure points, and is closest to the mean point of passing values.

Worst-case Point

Just knowing where this worst-case point is located will help guide where SPICE simulations should be made and even helps during analog yield optimizations. Failure rates can be estimated from worst-case distances. Different sampling methods at the worst-case point are introduced and compared. The First Order Reliability Model (FORM) is a straight line drawn through the worst-case point, and serves as a boundary between passing and failing regions.

First Order Reliability Model (FORM)

The error rate of using the FORM approximation is presented as a small number. The algorithms for finding the worst-case point are presented, and they show how few simulation runs are required to find 6-sigma values with small error values.

The shape of performance functions of the SRAM bit cell are shown to be continuous and only slightly non-linear, and using the FORM approach results in small errors. MunEDA has applied these high-sigma Worst Case Analysis (WCA) algorithms to its EDA tools resulting in the ability to scale to high-sigma levels like 5, 6 or even 7 sigma by only using a small number of simulation runs. The typical runtime for a 6.5 sigma SRAM bitcell analysis is completed in under 2 minutes, using just on CPU.

The MunEDA high-sigma methods are actually building models then used by Machine Learning (ML), which scale nicely to handle large circuits, like up to 110,000 mismatch parameters in a memory read-path analysis.

Cases where you still should run brute-force Monte Carlo analysis were presented: non-linearity, number of variables, complexity of test bench, low-sigma. Results from customer examples were shared that all used high-sigma analysis.

Summary

If you ever wondered how an EDA vendor like MunEDA approaches their results for high-sigma analysis, then this webinar is another must see. It covers the history of various analysis methods, and how MunEDA chose its worst-case point method. Real numbers are shared, so you know just how fast their tools operate.

Register for this MunEDA webinar scheduled for November 14th at 9AM PST, and be prepared to have your questions answered by the experts.

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Arm Total Design Hints at Accelerating Multi-Die Activity

Arm Total Design Hints at Accelerating Multi-Die Activity
by Bernard Murphy on 11-02-2023 at 6:00 am
Categories: AI, Arm, Automotive, Intel Foundry, IP, Samsung Foundry, Soitec, TSMC
2 Comments

multi die

I confess I am reading tea leaves in this blog, but why not? Arm recently announced Arm Total Design, an expansion of their Compute Subsystems (CSS) offering which made me wonder about the motivation behind this direction. They have a lot of blue-chip partners lined up for this program yet only a general pointer to multi-die systems and what applications might drive the need. Neither Arm nor their partners will make this investment simply for PR value, so I have to assume there is building activity they are not ready to announce. I’m guessing that in a still shaky economy the big silicon drivers (in hyperscalers, AI, automotive, and maybe communication infrastructure) are already engaged in faster and managed cost paths to differentiated custom silicon, likely in multi-die systems.

Arm CSS and Total Design

I wrote about CSS recently. CSS N2, as Arm describes it, is customizable compute subsystem that is configured, verified, validated and PPA-optimized by Arm. Think of a multi-core cluster objective for which you don’t just get the Lego pieces (CPU core, coherent interconnect, memory subsystem, etc.) but a complete customizable compute subsystem configured with up to 64 Neoverse N2 cores, multiple DDR5/LP DDR5 channels and multiple PCIe/CXL PHY/controller. All verified, validated, and PPA-optimized by Arm to a target foundry and process.

Most recently Arm revealed Arm Total Design, a comprehensive ecosystem of ASIC design houses, IP vendors, EDA tool providers, foundries, and firmware developers – to accelerate and simplify the development of Neoverse CSS-based systems. EDA tools and IP are supplied by Cadence, Synopsys, Rambus and of course Arm, among others. Design services come from companies including ADTechnology, Alphawave Semi, Broadcom, Capgemini, Faraday, Socionext and Sondrel. For silicon process and packaging technology they call out Intel Foundry Services and TSMC (though not Samsung curiously, maybe they are still working on that partnership). And AMI is in this ecosystem to provide software and firmware support.

Reading the tea leaves

I recently blogged on a Synopsys-hosted panel on multi-die systems which suggested already at least 100+ such systems in development. Representatives from Intel and Samsung voiced no objections to that estimate. At the same time there was consensus that these are technologies still very much in development, requiring close collaboration between system company, EDA, IP, chiplet, design services, foundry, and software development. This is not something that an in-house design team, even a hyperscaler design team, can handle on their own.

Arm mentions multi-die chiplet SoC designs in their release though in a fairly general way as the next frontier. I suspect the need is more pressing. Multi-die systems are becoming essential to support state of the art designs driven by the latest AI innovations, especially around transformer-based techniques. We already know that datacenters are pushing these technologies, automotive applications are looking for differentiation in improved natural language recognition and visual transformers for better global recognition, even wireless infrastructure sees application for more intelligent services and more efficient radio communication.

All these applications are pushing higher levels of integration between compute, accelerators and memory, the kind of integration which requires multi-die packaging. This demands experts from foundries to design services to EDA tooling. We also need a ramp-up in available high value chiplet designs, where the press release suggests another hint. Socionext have built a multi-core CPU chiplet around CSS and are aiming it at TSMC 2nm for markets in server CPUs, data center AI edge servers, and 5/6G infrastructure.

More momentum behind multi-die systems. You can read the press release HERE.

 

 

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Generative AI for Silicon Design – Article 2 (Debug My Waveform)

Generative AI for Silicon Design – Article 2 (Debug My Waveform)
by Anshul Jain on 11-01-2023 at 10:00 am
Categories: AI, EDA
1 Comment

Generative AI for Silicon Design Article 2

Generative AI has been making waves across various industries, and its potential continues to expand. Among its many applications, one particularly intriguing area is the capacity of GenAI to explain digital design waveforms and act as a co-pilot for hardware engineers in the debugging process. In this article, we will explore the fascinating possibilities that this technology brings to the table and its impact on the field of silicon development.

Experiment 2: Explaining Design Waveforms

This first experiment showcases the ability of Generative AI to recognise patterns and trends in data and revolutionise the way we understand and interact with waveforms. In this experiment, Google’s Generative AI Model – BARD was used to generate an explanation of write transfers in a system complying to AMBA APB protocol by looking at a sample waveform (sourced from https://documentation-service.arm.com)

Write transfer with wait states

Generated Explanation (tweaked to make its language inclusive)

Disclaimer: This explanation is not reviewed for accuracy

The waveform in the image shows the following signals:

TCLK: The APB3 clock signal.
PADDR: The APB3 address bus.
PWRITE: The APB3 write signal.
PSEL: The APB3 chip select signal.
PENABLE: The APB3 enable signal.
PWDATA: The APB3 write data bus.
PREADY: The APB3 ready signal.
Data 1: The data being written to the APB3 completer device.

The waveform shows the following behavior:

At time T1, the PWRITE signal goes high and the PADDR bus is driven with the address of the APB3 completer device to be written to.

At time T2, the PSEL signal goes high. This indicates that the APB3 initiator is ready to transfer data to the completer device.

At time T3, the PENABLE signal goes high. This indicates that the APB3 initiator is ready to drive the PWDATA bus.

At time T4, the PREADY signal goes high. This indicates that the APB3 completer device is ready to receive the data on the PWDATA bus.

At time T5, the PWRITE signal goes low. This indicates that the APB3 initiator has finished transferring data to the completer device.

The PSEL and PENABLE signals remain high until the APB3 completer device has finished processing the data.

What Does Future Look Like – GenAI Powered Debugger Copilot

One of the most exciting applications of generative AI is the potential it holds to be a co-pilot for developers during the debugging process. Waveforms are the lifeblood of complex systems in hardware design. A debugger copilot, powered by generative AI, can dissect waveforms, identify anomalies, and correlate patterns, making it an invaluable tool for engineers seeking to comprehend complex design behavior.

Challenges in Developing a Debugger Copilot

While the prospects of a debugger copilot powered by generative AI are enticing, there are challenges that need to be addressed. The accuracy and reliability of the AI’s explanations are paramount. We must ensure that the AI’s insights are trustworthy and not just algorithmically generated responses. Moreover, privacy and data security concerns are significant. Handling sensitive information in the debugging process requires a robust framework to protect data integrity.

Conclusion

The journey of generative AI into the realm of explaining waveforms and acting as a debugger copilot is an exciting one. This technology has the potential to transform the way we develop and debug software, saving time, reducing costs, and increasing accuracy. As engineers continue to explore its possibilities, the future of debugging looks promising.

Also Read:

Generative AI for Silicon Design – Article 1 (Code My FSM)

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WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration

WEBINAR: How to Achieve 95%+ Accurate Power Measurement During Architecture Exploration
by Daniel Nenni on 11-01-2023 at 6:00 am
Categories: Events, IP, Mirabilis Design

AVFS IP SOC

Today’s power modeling solutions are trained at measuring power using the micro-events captured from detailed RTL simulation or studying the electromagnetic radiation from IR drop and side channel attacks. These solutions are fantastic for debugging and verification of the implementation. There are both open source and commercial products for power modeling.  For example, Synopsys PrimeTime can provide the percentage of activity in a stage for each device while Cadence Joules can debug the power intent, and Ansys Totem can help with the transistor-level power integrity and reliability analysis.  There is an open-source power modelling add-on to SystemC. All of these are static solutions that take the simulation, process it and generate reports.  Alternately they work in conjunction with a debugger.

As the power requirements get more stringent and complex, designers need to predict the power consumption, impact of power intent and savings from power management units, during architecture exploration.  System designers and integrators want the power consumption metrics in the datasheet for the entire activity range, not just one or two scenarios.  The marketing team must be able to quickly generate power metrics for the requested scenarios. Thermal team requires heat and temperature data to plan for the cooling, chassis design and board layout.  The system integrators need guidelines on the battery lifecycle and peak power to plan for the supply and capacitance.  Thus, a good modelling solution must support power generation, storage, analog and digital consumption and power management. The IP or semiconductor vendor must have the ability share a dynamic model that quickly simulate scenarios. The accuracy of the power measurements at the architecture exploration must be within 10% of the value at RTL or board-level.

Power exploration starts by examining the tangible hardware and software choices that significantly affect SoC power consumption. These include:

  • Use cases
  • Architectural details (number of cores, choice of accelerators)
  • Power-saving features (DVFS, clock gating, power gating)
  • Firmware/software algorithms
  • Operating frequency and voltage modes
  • Process technology aspects that impact power

Modern SOCs employ multiple power management strategies either at individual IP level or full SOC level. One such strategy is adaptive voltage and frequency scaling (AVFS). In AVFS, a closed-loop feedback system is implemented between the voltage scaling power supply and delay-sensing performance monitor on the SoC. The on-chip performance monitor not only sees the actual voltage delivered on-chip but also understands whether the silicon is slow, typical or fast, and the effect of the temperature of the surrounding silicon. It can also track the utilization parameters to decide the choice of operating points.

The figure below represents an example of this feedback system between power manager and performance monitor on a chip.

System-level modelling solutions such as VisualSim Power Modeler 2.0 can be used to model the effect of power management strategies on the system performance and hence decide on a power-performance trade-off in early system design phases.

In the intricate realm of System-on-Chip (SoC) design, optimizing power is paramount. VisualSim Power Modeling 2.0 is a dynamic power exploration, optimization and measurement of the Intellectual Property, Semiconductor Device, embedded system, chassis or Data Center.  VisualSim enables system-level SoC power measurement even before delving into the intricacies of Register Transfer Level (RTL) development. Using this solution, designers and Power Architect can study ways to reduce power consumption, measure power consumed for a software application, impact of hardware configurations, adding of new hardware or change in the interconnect and new workloads/ use-cases. As the Power modeling toolkit is common from IP vendors to the system deployment, it is possible for suppliers and the system integrators to share encrypted power information along with the model.

VisualSim System-Level Power Modeling is used during the specification phase and before development.  Thus, it is possible to optimize the architecture to achieve Power-Performance-Trade off before development and also reuse the model for downstream debugging.

The built-AI engine continuously monitors the power activity to identify failures and identifies the cause of the failure.

See Webinar Replays Here
Also Read:

System Simulation, Architecture Exploration, Power Management, Performance Analysis

Mirabilis Invites System Architects at DAC 2023 in San Francisco

Mapping SysML to Hardware Architecture

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The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography
by Fred Chen on 10-31-2023 at 10:00 am
Categories: Lithography
1 Comment

Electron Beam Lithography

Electron beam lithography is commercially used to directly write submicron patterns onto advanced node masks. With the advent of EUV masks and nanometer-scale NIL (nanoimprint lithography), multi-beam writers are now being used, compensating the ultralow throughput of a single high-resolution electron beam with the use of over 100,000 beams [1-2]. Unlike optical or EUV scanners, the resolution is not determined by the numerical aperture (NA) of the system. Instead, it starts with how small the electron beam is focused, followed by how the electrons are subsequently scattered and release more electrons which are subsequently scattered.

Commonly, Gaussian functions are used to model the electron beam and scattering profiles. However, a single Gaussian function is not sufficient to build the effective point spread function. This is because the backscattered electrons travel far beyond the range of the immediately scattered electrons. At least two Gaussian functions (and generally more) are needed for an accurate profile. Some published results from the literature [3-4], in fact, indicate exponential functions as more appropriate for fitting the energy deposited by a high-energy electron beam. Compared to a Gaussian function, an exponential function has a sharper, narrower peak, a sharper drop-off, and a more extended tail.

Figure 1. Exponential functions more realistically describe the combination of a narrow beam with extended backscattering.

The narrow peak and sharp drop-off are consistent with the highest energy electrons (>>10 keV) not deviating far laterally from the entry point, while the extended tail comes from all the secondary electrons (many generations, no doubt) from electrons which are backscattered from the substrate.

The resolution limit from this point spread function can be studied (as in the optical cases) by considering the space between two exposed points. As may be expected, the shot noise from the electron dose plays a critical role (Figure 2).

Figure 2. Reducing the dose to 16% of the nominal value increases the impact from shot noise visibly. The two exposed spots here are separated by 40 nm. The number of Poisson events is considered proportional to the exponential deposited energy profile.

What also should not be a surprise is the impact of blur. Here blur comes from a wider range of electron energies (many keVs) than expected from EUV lithography (only up to ~92 eV).

Figure 3. Increasing blur reduces the peak-valley dose difference. Since the peak dose here is fixed, the valley dose is actually increasing with blur. As in Figure 2, the two exposed spots here are separated by 40 nm, and the number of Poisson events is considered proportional to the exponential deposited energy profile.

From Figure 3, we note two trends. First, the peak-valley dose difference diminished with increasing blur. Second, while the peak dose is fixed, the valley dose is increasing with increasing blur. In terms of the impact on stochastic dose variations, these two trends counter each other. The first trend increases sensitivity to fluctuations, but the second trend reduces the amplitude of such fluctuations in accordance with Poisson statistics. Consequently, the CD variation due to these fluctuations is comparable among the three cases (Figure 4).

Figure 4. CD variation for 20 points repeatability run, for the cases shown in Figure 3. The amount of variation is comparable among the three cases.

The 3 sigma uniformity is on the order of 3-4 nm (~15-20%) for the three cases examined. Obviously, the dose needs to be increased to reduce this to smaller values. However, this will proportionally increase write time if beam number is not increased; a doubling is considered unacceptable [2]. Larger CDs (>20 nm) will not be impacted as significantly [5], as the peak-valley difference is increased and more point spread functions are overlapped together in writing the spots [1,6]. However, for nanoimprint masks and High-NA EUV masks with subresolution assist features (SRAFs), the stochastic variations cannot be ignored.

References

[1] M. Tomandl et al., Proc. SPIE 12802, 1280204 (2023).

[2] C. Klein et al., Proc. SPIE PC12497, PC1249707 (2023).

[3] V. R. Manfrinato et al., Nano. Lett. 14, 4406 (2014).

[4] V. R. Manfrinato et al., Nano. Lett. 13, 1555 (2013).

[5] K. Ichimura et al., Proc. SPIE 12293, 122930Q (2022).

[6] K. Ichimura et al., Proc. SPIE 10584, 105840P (2018).

This article first appeared on LinkedIn Pulse: The Significance of Point Spread Functions with Stochastic Behavior in Electron-Beam Lithography

Also Read:

KLAC- OK quarter in ugly environment- Big China $ – Little Process $ – Legacy good

ASML- Longer Deeper Downcycle finally hits lithography – Flat 2024 – Weak Memory – Bottom?

ASML- Absolutely Solid Monopoly in Lithography- Ignoring hysteria & stupidity

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DVCon Europe is Coming Soon. Sign Up Now

DVCon Europe is Coming Soon. Sign Up Now
by Bernard Murphy on 10-31-2023 at 6:00 am
Categories: Accellera, AI, Automotive, Semiconductor Services

logo accellera min

I’m a fan of DVCon, a fan of Accellera and a fan of Munich, hosting DVCon Europe once again. This year’s event runs from November 14th through 15th (with some events on the 16th) at the Holiday Inn Munich in the City Center. Phillippe Notton (CEO, SiPearl) will deliver a keynote on “Energy Efficient High-Performance Computing in the Heart of Europe”, and Michaela Blott (Sr. Fellow at AMD Research) will deliver a second keynote on “Pervasive and Sustainable AI with Adaptive Computing”. Add to that a medley of Accellera updates and EDA, semiconductor, and EDA+semiconductor talks on a variety of topics. I’ll briefly summarize Accellera-related topics below, remembering that, as is normal with standards, detail is hard to come by until officially released. Remember to REGISTER.

Functional safety working group update

This working group is chaired by Alessandra Nardi, a well-respected authority in the safety domain. The group aims to standardize methods to capture and propagate safety intent from system (a car for example) down through software, SoC and IP design, ensuring ability to exchange data and to support traceability between multiple levels of total system design. This working group will release a white paper soon which they will discuss in the session.

Workshops on UVM-AMS and CDC/RDC

These are areas I am watching closely. In AMS, Accellera is working on both mixed signal modeling and UVM-AMS; in this event they will elaborate on the latter. This technical workshop will walk the audience through a worked example to illustrate key pieces of this approach and give a preview of how this standard will expand the ecosystem for AMS verification to allow vendors and users to create and share compatible verification components and use them in existing UVM environments. Well worth attending, I think.

The CDC/RDC (reset domain crossing) session starts with an intro to the basics on domain crossings. The second half will be another must-see for anyone working with IP verified against one CDC/RDC tool which must be verified at the system level using a different CDC/RDC tool. A demo will highlight different steps of the CDC verification flow. A small and illustrative RTL test case with at least two EDA verification tools will be used to raise awareness about the importance of a new standard to make CDC models portable and reusable between different tools.

IP-XACT and SystemC

IP-XACT has been around for a while and is well-accepted as a standardized format for IP meta data relevant to integration, but how widely is it used as an integration platform? The IP-XACT discussion comes in two parts, starting with a tutorial on the basics of the standard including aspects relevant to integration and the hardware/software interface. The second part addresses industrial practices from EDA vendors, IP providers, and IP integrators: Agnisys, Arteris, Infineon, and Intel. That I think should be very interesting – I’m always eager to hear more about IP-XACT integration practices in production.

There is also a SystemC evolution day planned to review upcoming standard advances and for experts in the field to network and exchange ideas.

AI panel (because AI)

You can’t have a conference these days without an AI topic. Accellera chair Lu Dai features as a panelist on this panel, titled “All AI All the Time”. They will discuss how AI can best be applied in verification objectives. I’m sure discussion will be fairly free ranging 😊

REGISTER before you forget!

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S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor

S2C’s FPGA Prototyping Accelerates the Iteration of XiangShan RISC-V Processor
by Daniel Nenni on 10-30-2023 at 10:00 am
Categories: EDA, Prototyping, S2C EDA

Pic1

S2C announced that the Beijing Institute of Open Source Chip (BOSC) adopted its Prodigy S7-19P Logic System, a VU19P-based FPGA prototyping solution, in the development of the “XiangShan” RISC-V processor. S7-19P not only accelerates the iterations of processor development but also simplifies other companies to realize XiangShan-based SoCs.

RISC-V, an open instruction set architecture, has increasingly become the focus of global processor development. Among them, “XiangShan” is a high-performance open-source RISC-V processor core and is considered an international leading representative of the RISC-V industry. Since the launch of its first generation, “XiangShan” has received over 2,500 stars and 277 forks on GitHub, making it one of the most followed open-source hardware projects internationally. To date, “XiangShan” has launched two generations, with the third generation under development. Industry-leading companies are adopting “XiangShan” and conducting further development for various applications and expanding the RISC-V ecosystem.

In the adoption of the “XiangShan” project, the key role of the Prodigy S7-19P Logic System is allowing software development and profiling in high-performance FPGA prototyping. This allows the software and hardware engineers of “XiangShan” to work in parallel, significantly shortening the development process. A BOSC representative added, “Due to the diversity of RISC-V, our clients need to survey different RISC-V cores to find the right one matching their applications. S2C’s FPGA prototyping enables us to showcase processor performance through the SPEC benchmark. It is also a must-have tool for I/O verification and BSP driver development. S2C’s solution covers the entire cycle from hardware design to software integration and client test drivers, making it easier for our clients to choose the most suitable solution and proliferation of the ‘XiangShan’ core.”

SPEC Benchmark:
SPEC benchmarking can verify whether the expected performance is achieved. By leveraging S2C’s Prodigy, the “XiangShan” team can conduct the performance evaluation by running Linux with a graphical interface. This provides the team with valuable feedback for more effective optimization.

I/O Verification:
S2C’s Prodigy provides an actual environment for testing and verifying all input/output communication channels in XiangShan. FPGA prototyping is used to ensure seamless integration and communication with other hardware components like memory, storage, and other interfaces. The “XiangShan” team has adopted various S2C’s daughter cards and interfaces, including flash, GMAC, and PCIe, and the overall system operates at 50MHz.

BSP Driver Development:
BSP (Board Support Package) driver development ensures smooth interaction between software and hardware. With FPGA prototyping, developers can develop and test the BSP on actual hardware, ensuring hardware-software co-development. This parallel approach thereby improves development efficiency and accuracy. Once the “XiangShan” hardware design is ported to S7-19P, the BOSC software team immediately embarks on BSP driver development. This method allows the software team to gain a deeper understanding of hardware features and limitations, ensuring optimized hardware design for “XiangShan” before the final tape-out and accelerating software development.

“‘XiangShan’ is a leading high-performance RISC-V processor core,” another BOSC representative stated, “S2C’s FPGA prototyping laid a solid foundation for the XiangShan project. We chose S2C because of their outstanding technology and services. They have injected great momentum into our project.”

Mr. Ying Chen, VP of Sales & Marketing at S2C, also commented, “We are glad that our Prodigy FPGA prototyping solutions accelerate the XiangShan project and meet a wide range of target market needs. In the future, we will work with more partners to expand the RISC-V community for the prosperity of the RISC-V ecosystem.”

About Beijing Institute of Open Source Chip
RISC-V has developed rapidly in recent years and become the focus of international scientific and technological competition. To improve China’s IC design level and build a technology platform connected with the international open source community, Beijing City and the Chinese Academy of Sciences have prioritized development in RISC-V, and organized a number of leading domestic enterprises and top scientific research institutes to establish the BOSC on December 6, 2021. The institute gathers the consensus of industrial development with open source and acceptance, stimulates application traction potential through collaborative innovation, and strives to promote integrating the RISC-V innovation chain and industrial chain, as well as accelerate industrialization in scientific and technological innovation achievements, and the creation of the world’s leading industrial ecosystem of RISC-V.

About S2C
S2C is a leading global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 600 customers, including 6 of the world’s top 10 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer’s SoC and ASIC verification needs. S2C has offices and sales representatives in the US, Europe, mainland China, Hong Kong, Korea, and Japan. For more information, please visit: www.s2cinc.com and more details about vu440, vu13p, vu19p board, vu9p FPGA, etc.

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Developing Effective Mixed Signal Models. Innovation in Verification

Developing Effective Mixed Signal Models. Innovation in Verification
by Bernard Murphy on 10-30-2023 at 6:00 am
Categories: Cadence, EDA

Innovation New

Mixed-signal modeling is becoming more important as interaction between digital and analog circuitry become more closely intertwined. This level of modeling depends critically on sufficiently accurate yet fast behavioral models for analog components. Paul Cunningham (Senior VP/GM, Verification at Cadence), Raúl Camposano (Silicon Catalyst, entrepreneur, former Synopsys CTO and now Silvaco CTO) and I continue our series on research ideas. As always, feedback welcome.

The Innovation

This month’s pick is Fast Validation of Mixed-Signal SoCs. The paper was presented in the 2021 Journal of the Solid-State Circuits Society. The authors are from Stanford, Seoul National University and Scientific Analog.

A recent SemiWiki blog on mixed signal captured enormous interest, suggesting this is an area worth further study. A critical step to realize effective mixed signal verification is to develop accurate mixed-level behavioral models for analog functions which are suitable for event-driven simulation, and even synthesizable models for deployment in hardware emulation. The paper describes a template-based approach to generating models and two methods to interpolate analog behavior to event-based connections: oversampling and event-driven modeling with feature vectors (real number models).

The authors demonstrate application to a high-speed link simulation and emulation with impressive results. Comparison between Spice and Verilog simulation on the ADC shows close correspondence in results, running orders of magnitude faster. Emulation-based modeling adds yet more orders of magnitude to that speed.

Paul’s view

Big context-swap this month into the world of analog verification and its “mixed-signal” intersection with digital verification. This paper is an invited paper in a prestigious journal which beautifully summarizes state-of-the-art to build abstracted models of analog circuits that can keep up with digital simulation, even on an emulator, and do so with amazingly good accuracy.

In the analog world everything is smooth and usually oscillating, with intended input-output behavior often described by first transforming input/output waveforms into the frequency domain. The gold standard for analog simulation is Spice, iteratively solving device-level differential equations for voltages at all points in a circuit within guaranteed error tolerances. Compared to digital simulation, Spice is thousands of times slower.

The typical approach to creating fast abstract analog models is to do discrete time sampling of the input waveform and then generate the appropriate discrete time sampled output waveform using some DSP-like logic (e.g. discrete-time filters). Signal values between these discrete time points can be generated if needed using linear or spline-based interpolation.

The authors present a complete open-source framework with an elegant model generation language and compiler to generate both simulatable and emulatable models from this language. They use an adaptive time-step sampling method with spline-based interpolation and work through a credible case study using their framework on a 16nm high speed SERDES link PHY. Going from Spice to digital CPU-based simulation with their abstracted models achieves a 13,000x speed-up. Putting the models on an FPGA gave another 300x speed-up. Nice.

Raúl’s view

The validation of mixed-signal SoCs is a challenge, among other things because running sufficient test vectors to validate the digital parts – typically with an event driven simulator or on an emulator – results in prohibitive times to simulate the analog part with a circuit simulator. A solution is the creation of analog behavioral models. This month’s paper reviews several approaches to create these models and presents what the authors believe to be the first complete, open-source framework for AMS emulation. This is an invited paper to the IEEE open journal of the Solid-State Circuits Society, and as such large passages read like a tutorial on analog design and validation. It is quite different to what we have done before in this blog; the reader needs some analog know-how to be able to fully benefit (e.g., Laplace domain, z-transform, PLL, phase interpolator, Nyquist rates, jitter, etc.).

Functional models of analog circuits receive inputs and generate outputs at discrete times. Waveforms can be modelled using piecewise constant or piecewise linear functions, using spline points (the approach used in this paper) or sums of complex exponential functions. Time is modelled as discrete-time (sampled or oversampled) or as piecewise linear modeling (used here). The actual models of circuits are assembled from a library of templates. The authors put all this together in a system consisting of: 1) A Python tool for generating synthesizable AMS models providing a set of functions that allows users to describe AMS blocks as differential equations, netlists, transfer functions, or switched systems, … in either fixed or floating point, and 2) A simulator-like abstraction of FPGA boards.. which provides emulation infrastructure that manages the emulation timestep, emulation clock speed, and test interfaces and generates the FPGA emulation bitstream with the help of EDA tools.

The trick is not using circuit simulation but rather replacing circuit models by functional models. For a high-speed link receiver called DragonPHY the speedup of a Verilog versus a Spice simulation is 12,800x, providing sufficient accuracy. But even this speedup is not enough to simulate the clock recovery and channel equalization loops, to test bit error rates (BER), with feedback loops which may take 100,000s of cycles to settle. Modifying the models so they are synthesizable and can be incorporated into emulation provides further 5000x speedup, sufficient to compute BER within 7.5%. Impressive!

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