SiC Forum2025 8 Static v3
Semiconductor Expert Forum

Posted on

Placement and Clocks for HPC

Placement and Clocks for HPC
by Paul McLellan on 10-11-2023 at 10:00 am
Categories: EDA, Siemens EDA

cts

You are probably familiar with the acronym PPA, which stands for Power/Performance/Area. Sometimes it is PPAC, where C is for cost, since there is more to cost than just area. For example, did you know that adding an additional metal layer to a chip dramatically increases the cost, sometimes by millions of dollars? It requires a minimum of two masks (interconnect, and vias) plus all the additional associated process steps. And interconnect layers normally come in pairs, vertical and horizontal, so usually it is four masks.

There are many inputs into optimizing PPAC, and a significant one is designing the clock tree. The clock can consume a lot of the power, and a lot of the interconnect, and obviously affects performance. The process of designing the clock tree is usually called Clock Tree Synthesis, usually abbreviated to CTS. Siemens EDA recently published a white paper Placement and CTS Techniques for High-Performance Computing Designs.

One challenge EDA tools face is that you only get the true quality of results when you have finished the design. In practice, this means that tools need to either use pessimism to guard band the results, or increase accuracy by having much better correlation between the tool in use and the final results.

The white paper discusses how to solve the placement and clock tree challenges in HPC designs using the Aprisa digital implementation solution, as these steps are fundamental to achieving the desired performance metrics during place and route. While most other place-and-route tools require waiting to post-route optimization to discover the true quality of the results, Aprisa offers users excellent correlation throughout the place-and-route implementation, which allows designers to gain confidence on the results much earlier in the flow at the placement and clock tree synthesis (CTS) stages. Aprisa is ideally suited to help designers deliver HPC IC innovations faster.

Aprisa is the Siemens digital implementation solution for hierarchical and block-level designs. Under the hood, it has a detail-route-centric architecture to reduce time to design closure, partly by pulling the implications of decisions early in the design process as opposed to waiting until the design is completed to find it has problems that were introduced earlier. A key to a modern implementation flow is to have consistent timing, extraction, DRC, and more across the whole flow.

Aprisa delivers optimal performance, power and area (PPA) for advanced nodes, and it has complete support for design methodologies and optimization to achieve both lowest power and highest performance.

The white paper uses an example design, an Arm Cortex-A76 in 5nm running at 2.75 GHz, and using 12 layers of metal for interconnect. I don’t have space here to go into the design in detail, you’ll have to read the white paper for a deeper dive.

The focus of the exercise was to analyze using 10 layers of metal versus 12 layers of metal (I said interconnect layers usually come in pairs already). The analysis revealed that, for the 10-layers option, the frequency would have to be lowered by 9 percent to achieve the desired power target. However, it resulted in significant cost savings for the entire project. Obviously, Aprisa cannot make the decision for you as to whether 9% performance hit is worth it to reduce the cost.

The focus of the white paper is clock tree synthesis (CTS), one of the big challenges in any HPC design. Aprisa supports useful skew, starting at placement optimization and continuing all the way to route optimization, to make certain that challenging design frequency targets are met. A strength of Aprisa CTS technology is that the push and pull offsets generated during placement optimization are realized during clock tree implementation.

Clocks generally go to flip-flops, and an optimization that modern cell libraries include are multi-bit flip-flops with a common clock. Aprisa has the capability to merge or demerge multi-bit flip-flops and clone/declone integrated clock gates. Aprisa does this based on the timing, physical location of the cells and criticality of the paths.

Post-CTS optimization in Aprisa includes congestion recovery that recovers congestion created during clock tree synthesis. Congestion recovery is a clock-aware approach that does not degrade timing and so reduces iterations back to placement optimization that otherwise would be required.

Aprisa supports different types of clock tree structures such as H-tree, multi-point CTS and custom mesh. Multi-point is the most popular approach for HPC designs and is the one described in the white paper.

There is a lot more to an implementation flow than synthesizing the clock tree, of course! But CTS is a critical stage, especially for demanding HPC designs, because there is so little room for deviation to achieve the desired performance and meet PPA requirements.

Aprisa is certified by the top foundries for the most advanced nodes. It ensures all PPA metrics are carefully balanced for HPC design implementation through high-quality clock trees. Not to  mention placement and routing technologies that reduce timing closure friction between the block and top-level during assembly.

Once again, the white paper can be downloaded here.

Also Read:

AI for the design of Custom, Analog Mixed-Signal ICs

Optimizing Shift-Left Physical Verification Flows with Calibre

Reducing Electronic Systems Design Complexity with AI

Posted on

Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge

Long-standing Roadblock to Viable L4/L5 Autonomous Driving and Generative AI Inference at the Edge
by Lauro Rizzatti on 10-11-2023 at 6:00 am
Categories: AI, Automotive

Table I

Two recent software-based algorithmic technologies –– autonomous driving (ADAS/AD) and generative AI (GenAI) –– are keeping the semiconductor engineering community up at night.

While ADAS at Level 2 and Level 3 are on track, AD at Levels 4 and 5 are far from reality, causing a drop in venture capital enthusiasm and money. Today, GenAI gets the attention, and VCs eagerly invest billions of dollars.

Both technologies are based on modern, complex algorithms. The processing of their training and inference shares a few attributes, some critical, others important but not essential: See table I.

Table I caption: Algorithm training and inference share some but not all critical attributes. Source: VSORA

The remarkable software progress in these technologies has until now not been replicated by advancements in algorithmic hardware to accelerate their execution. For example, state-of-the-art algorithmic processors do not have the performance to answer ChatGPT-4 queries in one or two seconds at a cost of ¢2 per query, the benchmark established by Google search, or to process the massive data collected by the AD sensors in less than 20 milliseconds.

That is until French startup VSORA invested brainpower to address the memory bottleneck known as the memory wall.

The Memory Wall

The memory wall of the CPU was first described by Wulf and McKee in 1994. Ever since, memory accesses have become the bottleneck of computing performance. Advancements in processor performance have not been mirrored in memory access progress, driving processors to wait ever longer for data delivered by memories. At the end, processor efficiency drops way below 100% utilization.

To solve the problem, the semiconductor industry created a multi-level hierarchical memory structure with multiple levels of cache nearer the processor that reduces the amount of traffic with the slower main and external memories.

Performance of AD and GenAI processors depends more than other types of computing devices on wide memory bandwidth.

VSORA, founded in 2015 to target 5G applications, invented a patented architecture that collapses the hierarchical memory structure into a large high bandwidth, tightly coupled memory (TCM) accessed in one clock cycle.

From the perspective of the processor cores, the TCM looks and acts like a sea of registers in the amount of MBytes versus kBytes of actual physical registers. The ability to access any memory cell in the TMC in one cycle yields high execution speed, low latency, and low-power consumption. It also requires less silicon area. Loading new data from external memory into the TCM while the current data is processed does not affect system throughput. Basically, the architecture allows for 80+% utilization of the processing units through its design. Still, there is a possibility to add cache and scratchpad memory if a system designer so wishes. See figure 1.

Figure 1 caption: The traditional hierarchical memory structure is dense and complicated. VSORA’s approach is streamlined and hierarchical.

Through a register-like memory structure implemented in virtually all memories across all applications, the advantage of the VSORA memory approach cannot be overstated. Typically, cutting-edge GenAI processors deliver single digits percentage efficiency. For instance, a GenAI processor with nominal throughput of one Petaflops of nominal performance but less than 5% efficiency delivers usable performance of less than 50 Teraflops. Instead, the VSORA architecture achieves more than 10 times greater efficiency.

VSORA’s Algorithmic Accelerators

VSORA introduced two classes of algorithmic accelerators –– the Tyr family for AD applications and the Jotunn family for GenAI acceleration. Both deliver stellar throughput, minimal latency, low-power consumption in a small silicon footprint.

With nominal performance of up to three Petaflops, they boast a typical implementation efficiency of 50-80% regardless of algorithm type, and a peak power consumption of 30 Watts/Petaflops. These are stellar attributes, not reported by any competitive AI accelerator yet.

Tyr and Jotunn are fully programmable and integrate AI and DSP capabilities, albeit in different amounts, and support on-the-fly selection of arithmetic from 8-bit to 64-bit either integer or floating-point based. Their programmability accommodates a universe of algorithms, making them algorithm agnostic. Several different types of sparsity are also supported.

VSORA processors’ attributes propel them to forefront of the competitive algorithmic processing landscape.

VSORA Supporting Software

VSORA designed a unique compilation/validation platform tailored to its hardware architecture to ensure its complex, high-performance SoC devices have plenty of software support.

Meant to put the algorithmic designer in the cockpit, a range of hierarchical verification/validation levels –– ESL, hybrid, RTL and gate –– deliver push-button feedback to the algorithmic engineer in response to design space explorations. This helps him or her select the best compromise between performance, latency, power and area. Programming code written at a high level of abstraction can be mapped targeting different processing cores transparently to the user.

Interfacing between cores can be implemented within the same silicon, between chips on the same PCB or through an IP connection. Synchronization between cores is managed automatically at compilation time and does not require real-time software operations.

Roadblock to L4/L5 Autonomous Driving and Generative AI Inference at the Edge

A successful solution should also include in-field programmability. Algorithms evolve rapidly, driven by new ideas that obsolete overnight yesterday’s state of the art. The ability to upgrade an algorithm in the field is a noteworthy advantage.

While hyperscale companies have been assembling huge compute farms with multitudes of their highest performance processors to handle advanced software algorithms, the approach is only practical for training, not for inference at the edge.

Training is typically based on 32-bit or 64-bit floating-point arithmetic that generates large data volumes. It does not impose stringent latency and tolerates high-power consumption as well as substantial cost.

Inference at the edge is typically performed on 8-bit floating-point arithmetic that generates somewhat less amounts of data, but mandates uncompromising latency, low energy consumption, and low cost.

Impact of Energy Consumption on Latency and Efficiency

Power consumption in CMOS ICs is dominated by data movement not data processing.

A Stanford University study led by Professor Mark Horowitz showed that the power consumption of memory access consumes orders of magnitude more energy than basic digital logic computations. See table II.

Table II Caption: Adders and multipliers dissipate from less than one Picojoule when using integer arithmetic to a few Picojoule when processing floating point arithmetic. The energy spent accessing data in cache jumps one order of magnitude to 20-100 PicoJoule and up to three orders of magnitude to over 1,000 PicoJoule when data is accessed in DRAM. Source: Stanford University.

AD and GenAI accelerators are prime examples of devices dominated by data movement posing a challenge to contain power consumption.

Conclusion

AD and GenAI inference pose non-trivial challenges to achieve successful implementations. VSORA can deliver a comprehensive hardware solution and supporting software to meet all critical requirements to handle AD L4/L5 and GenAI like GPT-4 acceleration at commercially viable costs.

More details about VSORA and its Tyr and Jotunn can be found at www.vsora.com.

About Lauro Rizzatti

Lauro Rizzatti is a business advisor to VSORA, an innovative startup offering silicon IP solutions and silicon chips, and a noted verification consultant and industry expert on hardware emulation. Previously, he held positions in management, product marketing, technical marketing and engineering.

Also Read:

Soitec is Engineering the Future of the Semiconductor Industry

ISO 21434 for Cybersecurity-Aware SoC Development

Predictive Maintenance in the Context of Automotive Functional Safety

Posted on

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem

Synopsys – TSMC Collaboration Unleashes Innovation for TSMC OIP Ecosystem
by Kalar Rajendiran on 10-10-2023 at 10:00 am
Categories: AI, Automotive, EDA, Foundries, IP, Synopsys

L.C. OIP 2023

As the focal point of the TSMC OIP ecosystem, TSMC has been driving important initiatives over the last few years to bring multi-die systems to the mainstream. As the world is moving quickly toward Generative AI technology and AI-based systems, multi-die and chiplet-based implementations are becoming essential. TSMC recently hosted its annual Open Innovation Platform (OIP) Ecosystem Forum in Santa Clara, CA. During the keynote address, TSMC executives highlighted the significant advances that have been accomplished through ecosystem alliances and collaborative efforts since last year’s event.

Specifically, significant strides have been made in multi-die system innovation initiatives, including the unveiling of 3Dblox 2.0 (the 3rd generation of 3Dblox), the formation of 3Dblox committee and the expansion of its 3DFabric Alliance to 21 partners. The 3Dblox Committee is an independent standard group aimed at creating industry-wide specifications for system design with chiplets from any vendor. The 3DFabric Alliance now has subgroups collaborating on design, memory, substrate, testing, manufacturing and packaging. These developments highlight TSMC’s commitment to advancing 3D IC technologies and fostering industry collaboration to drive innovation in AI, HPC, and mobile applications. And the commitment is reflected in the following quote from Dr. L.C. Lu, TSMC fellow and vice president of Design and Technology Platform. “As our sustained collaboration with OIP ecosystem partners continues to flourish, we’re enabling customers to harness TSMC’s leading process and 3DFabric technologies to reach an entirely new level of performance and power efficiency for the next-generation artificial intelligence (AI), high-performance computing (HPC), and mobile applications.”

Synopsys Spotlight

The event was marked by many insightful presentations that showcased the collaborative efforts between TSMC and various OIP ecosystem partners in accelerating semiconductor innovation. As the Silicon to Software™ partner for companies developing electronic products and software applications, Synopsys made a number of announcements recently. This article shines a spotlight on how Synopsys’ collaborative efforts with TSMC and other ecosystem partners unleashes innovation for customers as well as the entire ecosystem.

Certified Flows for TSMC N2 Process Accelerate 2nm Innovation

Synopsys partnered with TSMC to fast-track advanced-node System-on-Chip (SoC) designs on TSMC’s N2 process technology. Key highlights of the collaboration include certified design flows, powered by Synopsys.ai™ for improved productivity and IP portfolio development for HPC, AI, and mobile applications. AI-driven design optimization with Synopsys DSO.ai™ aims to enhance power efficiency, performance, and chip density.

“The Synopsys digital and analog design flows for the TSMC N2 process represent a significant investment by Synopsys across the full EDA stack,” said Sanjay Bali, vice president of strategy and product management for EDA at Synopsys. “This helps designers jumpstart their N2 designs, differentiate their SoCs with increasingly better power, performance, and chip density, and accelerate their time to market.”

Dan Kochpatcharin, Head of Design Infrastructure Management Division at TSMC, emphasized delivering high-quality results and faster time to market as the hallmarks of the longstanding collaboration between Synopsys and TSMC. This collaboration showcases Synopsys’ commitment to comprehensive EDA and IP solutions, supporting innovation and competitiveness. For example, below are some of the methodology innovations and Fusion Compiler innovations that are the results of Synopsys’ collaboration with TSMC. When moving from N3E to N2, power grid impacted routability ratio. Synopsys worked with TSMC to improve it and reduce the impact to less than 2% compared to N3E. Synopsys updated its clock tree synthesis methodology to be able to handle the wider clock library cells in N2. The company upgraded its Fusion Compiler tool to become vertically aware to accommodate N2’s multiple double height cells with different OD for scaling speed and power.

You can find the full news release related to the above, here.

AI-Driven Analog Design Migration Flow for TSMC’s Advanced Process Technologies (N2, N3E, N4P and many others)

Synopsys expanded its analog design migration flow to cover TSMC’s advanced process technologies, including N4P, N3E, and N2. This flow, part of the Synopsys Custom Design Family, incorporates AI-driven circuit optimization, reducing manual effort and improving design quality. It includes interoperable process design kits (iPDKs) for TSMC FinFET nodes and an RF design reference flow for Radio Frequency Integrated Circuit (RFIC) designs. Sanjay Bali from Synopsys stressed the importance of AI-driven solutions in complex chip design and how customers can unlock massive productivity gains with efficient migration of their designs from node-to-node.

Dan Kochpatcharin from TSMC highlighted the significant performance and power efficiency advantages of TSMC’s advanced processes and the benefits of migrating existing analog designs to them.

You can find the full news release related to the above, here.

Broadest Portfolio of Automotive-Grade IP on TSMC N5A Process

Synopsys has introduced a comprehensive portfolio of automotive-grade Interface and Foundation IP designed for TSMC’s N5A process. This IP is tailored to meet the demanding requirements of automotive System-on-Chip (SoCs) in terms of reliability and high-performance computing. It includes logic libraries, embedded memories, GPIOs, SLM PVT monitors, and PHYs for LPDDR5X/5/4X, PCIe 4.0/5.0, 10G USXGMII Ethernet, MIPI C-PHY/D-PHY and M-PHY, and USB. The portfolio adheres to the ISO 26262 standard for random hardware faults, facilitating the development of safety-critical SoCs for applications like advanced driver assistance systems (ADAS) and highly automated driving (HAD) systems.

“New generations of automotive SoC designs will need to support massive amounts of safety-critical data processed at extreme speeds and with high reliability,” said John Koeter, senior vice president of marketing and strategy for IP at Synopsys. “Synopsys’ high-quality, automotive-grade Interface and Foundation IP on TSMC’s N5A process enables automotive OEMs, Tier 1s, and semiconductor companies to minimize IP integration risk and help meet the required functional safety, performance, and reliability levels for their SoCs.”

During a chat with John, he pointed to how electrification of automobiles is driving massive demand for automotive IP.  And while EVs are just 15% of the market today, they are projected to make 2/3rds of the market by 2030. The OIP collaboration between Synopsys and TSMC supports this evolution of software-defined vehicles, enabling the processing of large volumes of safety-critical data with high reliability and performance.

You can find the full news release related to the above, here.

Optimized Multi-Die System Design Solution for Higher Quality of Results

Synopsys has expanded its collaboration with TSMC to enhance multi-die system designs. It has introduced a solution supporting the 3Dblox 2.0 standard and TSMC’s 3DFabric™ technologies. Key elements include the unified exploration-to-signoff platform, 3DIC Compiler, which streamlines multi-die system design, and UCIe PHY IP, which achieved first-pass silicon success on TSMC’s N3E process, facilitating low-latency, low-power, high-bandwidth connectivity between dies. This collaboration addresses the challenges in high-performance computing, data center, and automotive applications, offering a comprehensive and scalable solution for optimized multi-die system designs.

“There’s a lot of work to be done to make multi-die systems a reality,” said Koeter. “Working closely with TSMC in many different areas is really key to executing and helping the industry to move to this new level of complexity.”

You can find the full news release related to the above, here.

Accelerating RFIC Design with Reference Flow for TSMC N4PRF Process

Synopsys joined forces with Keysight Technologies and Ansys to introduce a new reference flow for TSMC N4PRF, a cutting-edge 4-nanometer (nm) radio frequency (RF) FinFET process technology. This collaboration addresses the growing complexity of RF integrated circuit design in next-gen wireless systems (WiFi-7 systems), which demand higher bandwidth, lower latency, and broader coverage. The reference flow, based on the Synopsys Custom Design Family, provides an open RF design environment with higher predictive accuracy and productivity. It integrates with Keysight’s RFIC design and electromagnetic analysis tools and incorporates Ansys’ EM modeling and signoff power integrity solutions. The outcome of this collaboration empowers RF designers to tackle the challenges of designing advanced RFICs for high-performance wireless systems.

You can find the full news release related to the above, here.

Summary

The TSMC OIP Ecosystem Forum showcased the power of collaboration within the semiconductor ecosystem, with companies from various disciplines demonstrating their offerings leveraging TSMC’s technology. This article spotlighted the results from various collaborative efforts between Synopsys and TSMC as publicized through different news releases leading to the OIP Ecosystem Forum event. It is clear that Synopsys’ collaborative and development oriented investments and efforts are well aligned to its overarching Synopsys.ai and 3DIC initiatives to support futuristic electronic systems. And that in turn serves the TSMC OIP ecosystem well and helps unleash next-generation innovations.

To learn more, visit www.Synopsys.com.

Also Read:

Transformers Transforming the Field of Computer Vision

The True Power of the TSMC Ecosystem!

TSMC’s First US Fab

Posted on

Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design

Disaggregated Systems: Enabling Computing with UCIe Interconnect and Chiplets-Based Design
by Kalar Rajendiran on 10-10-2023 at 6:00 am
Categories: Alphawave Semi, Chiplet, IP

AresCORE UCIe PHY Support for All Package Types

The world of computing is evolving rapidly, with a constant demand for more powerful and efficient systems. Generative AI has driven exponential growth in the amount of data that is generated and processed at very high data speeds and very low latencies. Traditionally, computing systems have been built using monolithic designs, where all components, such as the central processing unit (CPU), memory, and I/O interfaces, are integrated onto a single monolithic die. While this approach has served us well for many years, it has limitations in terms of scalability, power efficiency, and flexibility. This is where chiplets come into play.

Chiplets are smaller, modular semiconductor components that can be designed and manufactured independently. These chiplets can serve various functions, such as CPUs, GPUs, accelerators, memory controllers, and I/O interfaces. By breaking down the monolithic design into these smaller building blocks, chiplets offer several advantages. This concept of breaking down traditional monolithic computing architectures into chiplets leads to what is termed a disaggregated system. In addition to lower NRE, lower power and smaller die, disaggregated systems enable easier upgradability and scalability as per workload/application requirements. This approach also results in improved yield and cost efficiency and enhanced system performance and energy efficiency.

UCIe Interconnect

While chiplets-based designs bring several benefits, they also present a challenge, which is the issue of efficiently interconnecting these chiplets to create a cohesive computing system.  The Universal Chiplet Interconnect Architecture (UCIe) addresses this challenge. UCIe is a standardized interconnect technology designed to provide high-speed, low-latency communication between chiplets and the motherboard. It serves as the glue that binds chiplets together, ensuring they can work seamlessly as a unified system.  It enables energy efficiency, high bandwidth density, low end-to-end latency, and robustness.

Use Cases

Disaggregated systems enable data center operators to tailor their computing resources to specific workloads, improving resource utilization and energy efficiency. This is especially valuable in cloud computing environments. High performance computing clusters can benefit from the flexibility of chiplets, allowing for specialized accelerators to be added or replaced as needed, maximizing computational power. In edge computing deployments, where space and power constraints are significant, disaggregated systems can be customized for specific edge applications, such as AI inference or data processing.

At the Recent TSMC Open Innovation Platform (OIP) Ecosystem Forum

At the most recent TSMC OIP Ecosystem Forum, there were many interesting presentations from various ecosystem partners. One presentation that covered the topic of disaggregated systems was from Letizia Giuliano of Alphawave Semi.

UCIe Complete Solution from Alphawave Semi

At the physical layer, the solution includes an Electrical PHY (AFE) that leverages silicon-proven analog IP. This component handles essential functions like clocking, link training, and sideband signals. Additionally, it incorporates a Logical PHY with Multi-Module PHY logic, providing a top-level floorplan for flexible package options.

The UCIe Die-to-Die (D2D) Adapter ensures smooth D2D interconnectivity. It manages link state, negotiates parameters crucial for chiplet interoperability, and ensures a reliable link by implementing CRC and link-level retry mechanisms. At the protocol layer, the solution natively maps PCIe and CXL protocols via Flit-Aware Mode and offers a Streaming Protocol Bridge for diverse SoC interfaces. Furthermore, Alphawave Semi provides a comprehensive platform for electrical, physical form factor, and protocol compliance, along with a complete set of test vehicles to facilitate interoperability testing.

Together, the above components enable a robust and complete UCIe solution, addressing various aspects of die-to-die chiplet integration and ensuring seamless functionality support for disaggregated systems.

Summary

Chiplets have emerged as a game-changer in the world of System-on-Chip (SoC) design, especially within advanced manufacturing nodes. Compared to traditional technologies, chiplets offer significant advantages, allowing for diverse SoC design structures. A robust and open chiplet ecosystem relies on Interface IPs and the UCIe Die-to-Die (D2D) standard is fostering such an open ecosystem. It facilitates seamless communication between chiplets from different manufacturers, ensuring compatibility and interoperability. Additionally, the integration of higher-level packaging takes chiplets to a new level, offering a wide range of utilization scenarios.

As a forward-thinking industry player, Alphawave Semi provides comprehensive D2D IP Subsystem Solutions, application optimized Chiplet Architectures and complete custom silicon solutions on leading edge nodes down to 3nm, to meet the needs of future System-in-Packages (SiPs). As a long-standing partner of TSMC in the Open Innovation Platform®, Alphawave Semi is very active in TSMC’s IP Alliance, Virtual Channel Aggregator (VCA), Design Center Alliance (DCA) and the new 3DFabricTM Alliance.

To learn more, visit

Chiplets

D2D Subsystem

Advanced Packaging

Custom Silicon

Also Read:

Interface IP in 2022: 22% YoY growth still data-centric driven

Alphawave Semi Visit at #60DAC

Coherent Optics: Synergistic for Telecom, DCI and Inter-Satellite Networks

Posted on

Can Generative AI Recharge Phone Markets?

Can Generative AI Recharge Phone Markets?
by Bernard Murphy on 10-09-2023 at 10:00 am
Categories: AI, Mobile

Consensus on smartphone markets hovers somewhere between slight decline and slight growth indicating lack of obvious drivers for more robust growth. As a business opportunity this unappealing state is somewhat offset by sheer volume ($500B in 2023 according to one source) but we’re already close to peak adoption outside of China so the real question for phone makers must be “what is the next killer app that could move the needle?”

We consumers are a fickle lot and entertainment seems to rank high on our list of must-haves. Arm is betting on mobile gaming. Another possibility might be generative AI for image creation/manipulation. Qualcomm has already demonstrated a phone based capability while others including Apple are still focused on large language model apps. For me it’s worth looking closer at the image aspect of generative AI simply to be a little more knowledgeable if and when this takes off. For fun I generated the image here using Image Creator from Microsoft Bing.

Diffusion-based generation

I am going to attempt to explain the concept by comparing with an LLM. LLMs train on text sequences, necessarily linear. Lots of it. And they work on tokenized text, learning when they see a certain sequence of tokens what might commonly follow that sequence. Great for text but not images which are 2D and generally not tokenizable, so the training approach must be different. In diffusion-based training, first noise is progressively added to training images (forward diffusion), while the network is trained by denoising modified images images to recover each original image (reverse diffusion). Sounds messy but apparently the denoising method (solving stochastic differential equations) is well-defined and robust. The Stable Diffusion model, as one example, is publicly available.

It is then possible to generate new images from this trained network, starting from a random noise image. Now you need a method to guide what image you want to generate. Dall.E-2, Midjourney, and Stable Diffusion can all take text prompts. These depend on training taken from text labels provided along with the training images. Inference then includes prompt information in the attention process in the path to inferring a final image. Like LLMs these systems also use transformers which means that support for this capability requires new hardware.

Generation is not limited to creating images from scratch. A technique called inpainting can be used to improve or replace portions of an image. Think of this as an AI-based version of the image editing already popular on smartphones. Not just basic color, light balance, cropping out photobombs, etc but fixing much more challenging problems or redrafting yourself in cosplay outfits – anything. Now that I can see being very popular.

Will generative AI move the needle?

I have no idea – see above comment on fickle consumers. Then again, visual stimulus, especially around ourselves, and play appeals to almost everyone. If you can do this on your phone, why not? AI is a fast-moving domain which seems to encourage big bets. I certainly wouldn’t want to bet against this possibility.

I should also mention that generative imaging already has more serious applications, especially in the medical field where it can be used to repair a noisy CAT scan or recover details potentially blocked by bone structure. I can even imagine this technology working its way into the forensics toolkit. We’ve all seen the TV shows – Abby or Angela fill in missing details in a photograph by extrapolating with trained data from what is visible. Generative imaging could make that possible!

Posted on

SPIE- EUV & Photomask conference- Anticipating High NA- Mask Size Matters- China

SPIE- EUV & Photomask conference- Anticipating High NA- Mask Size Matters- China
by Robert Maire on 10-09-2023 at 6:00 am
Categories: Chiplet, Events, Lithography, Semiconductor Advisors, Semiconductor Services

Conference EUV Lithography

– SPIE EUV & Photomask conference well attended with great talks
– Chip industry focused on next gen High NA EUV & what it impacts
– Do big chips=big masks? Another Actinic tool?
– AI & chip tools, a game changer- China pre-empting more sanctions

The SPIE EUV & Photomask conference in Monterey California

Both the weather and the crowds were great at the conference with what appeared to be record attendance amidst excellent presentations. For an industry that is in the middle of an ugly down cycle, there were a lot of people there in a very positive mood. It seemed more than double from Covid lows.

It was all about anticipation of High-NA EUV – due by end of year

Much of the conference, presentations and discussion was about the soon to be shipped (rumored to be about $400M) High-NA EUV tool by ASML.

What it means for the industry both in terms of promise and problems associated with it and what is being done to prepare for it.

Unlike the roll out of the first generation of EUV tools which seemed to take forever, was mired with problems and was somewhat anti-climatic after it finally arrived it feels like the industry may have a better handle on it this time around.

We also think that ASML is clearly doing a better job with less said perhaps working better.

Of course we haven’t yet had one shipped let alone installed and working. Even though it is significantly different from first gen tools, there is likely enough commonality to smooth the way a bit.

Are bigger Masks better? and needed?

One of the key problems with high NA EUV tools is that the new optics limits the size of the print area on the wafer (the die).

This means that chip size is limited and half that of current EUV & DUV scanners. Unfortunately the industry is moving in the opposite direction with ever larger chips needed to fill the compute power hungry applications like AI. Many current Nvidia chips could not be printed as is with High-NA scanners.

The fix that is most often talked about is “stitching” together two fields/two prints to print one whole chip. Imagine trying to print a single photograph from two negatives adjacent to one another to produce a seamless picture- its really, really hard.

Now try doing it with nanometer scale, atomic precision so that electronic circuitry lines up seamlessly- not at all easy- but needs to be done due to the limits of High NA.

Obviously the move to chiplets works well as a solution but not everything lends itself to that solution.

The pre-game show

Sunday, before the conference, a large semiconductor manufacturer gathered their key suppliers in a room to convince them, push them, and get commitments from them to adopt bigger photomasks which will allow High NA scanners to print bigger chips thus helping to fix the High-NA tiny chip problem (somewhat).

The proposal is to double the current 6X6 Photomask (negative) to a 6X12 size which would work in a High-NA scanner.

This is not as easy as it sounds but would obviously be the most elegant fix of the High NA small print problem. Essentially the entire photomask industry supply chain would have to change.

Probably easiest for mask writers and inspection tools from Lasertec and KLA but harder on “blank” makers who produce the blank photomasks.

This certainly has generated quite a bit of controversy as neither stitching nor bigger masks are easy but one is certainly more elegant.

Another Actinic Mask inspection tool to compete with Lasertec monopoly? But not from KLA….

From the conference, rumor has it, that Zeiss (the famous maker of all ASML’s lenses) will be making an actinic (EUV wavelength) mask inspection tool.

This seems to make sense as they have been making an “AIMS” EUV mask “review” tool, which finally seems to acceptable to the industry after a difficult start. Zeiss obviously knows how to make critical EUV lenses, and the industry would like more than one supplier.

But what about KLA?……Crickets….

KLA has been radio silent about its long lost/overdue actinic tool. While Lasertec had a nice presentation at the conference about their actinic tool there wasn’t anything from KLA.

The industry is clearly not fully satisfied with E-Beam mask inspection or using DUV technology or “print and pray” using wafer inspection they want the “real thing”…actinic pattered mask inspection (APMI).

AI’s impact on semiconductor equipment tools

We have been wondering where there will be impact on semiconductor tools makers from the AI revolution.

Metrology and inspection tools made by companies like KLA, AMAT, ONTO, Nova and many others consist of a light source to illuminate a target, optics to capture the image and millions of lines of code to analyze the image to provide useful information to the user.

While the illumination source and optics are difficult and complex in many cases they are likely not the competitive “moat” that millions of lines of image analysis code written over decades is. It seems much if not most of the value of measuring and/or inspecting semiconductors is determining what’s in the picture of the chip not taking the picture of the chip.

As an example, doing a “die to die” comparison of a known good chip to a chip under question gets a lot easier with today’s AI.

As both the chips and the photomasks that they are printed from, get more complex, more advanced AI is changing the industry.

But it is also likely democratizing it. It is likely a lot easier with AI tools to analyze these highly complex images, you don’t need millions of lines of custom code written over decades. From what we have heard, many chip makers, especially the large ones, have put a significant effort into this and may rival in some cases what is available from tools makers.

It also allows new start ups, especially those with AI expertise (such as China) to develop new tools, more quickly or replace existing or sanctioned tools.

If a chip maker says to a tool maker “just give me an image, I’ll do my own analysis”, what does that do to the value of tools?

Is China preempting new sanctions? Gina is pissed!

While China continues to buy whatever they can get their hands on, they seem to be planning on losing more access to US tools and are getting ahead of the problem. As an example, we have heard that while China continues to buy KLA inspection tools they have also been buying less capable non US tools which they might not have otherwise bought but perhaps assume they will be able to get them for longer than the US tools.

It seems more than blatantly clear that new sanctions are coming on or about the one year anniversary of tool sanctions last October.

China all but spit in Gina Raimondo’s face by announcing a 7NM chip while she was visiting China. The timing seems that China was certainly daring her to put more restrictions in place and she will clearly oblige them.

Gina Raimondo yesterday said she needs more “tools” (read that as sanctions) to control China chips. She said “it was incredibly disturbing” (the progress that China has obviously made in the face of sanctions).

The only thing that may hold back nuclear Armageddon chip sanctions is Biden meeting with Xi in November.

5NM is next for China…will they get to 3NM?

As we pointed out in a prior report, we were not surprised that China got a 7NM chip out. We also fully expect them to put out a 5NM chip. The sanctions on EUV are clearly inadequate and any other sanctions are clearly very porous. ASML still has many DUV tools in the pipeline destined for China and AMAT, LRCX and KLAC still have China as their best customer.

Maybe the US should stop what’s in the pipeline before it gets shipped. Tool makers will scream bloody murder and they will double down on expensive lobbyists in Washington to press for relief.

Its unclear how far things will go but its safe to say more sanctions than we have now otherwise the US should just surrender and ship anything China wants.

Getting to 5NM is a forgone conclusion and embarrassment. The open question is can they keep going and how far? There are some clear indications that 3NM is not entirely out of reach with their existing DUV tools and a lot of effort and cost.

Where there’s a will, there’s a way……..

Sanctions have forgotten about all the existing tools in China

All we seem to hear about are sanctions on shipping new tools to China. But what about all those US manufactured tools and technology that are currently pumping out 7NM chips in China?

Maybe sanctions should and will contain language about service, spare parts, upgrades and all things that keep the offending tools working.

What about sending US people to China to fix & service tools and process problems? Hopefully, those in Washington will figure out that its not just new tools but all the tools that were previously shipped (in such large volumes). As we have seen in a past examples, when service & support is withdrawn, fabs collapse quickly.

The stocks

We think semiconductor equipment stocks are in for a rough earnings season. The downcycle is clearly going deeper into 2024. Memory still sucks. TSMC is slowing Arizona, not due to labor or other false excuses but because demand is weak. Utilization rates are low for TSMC and way worse for second tier players like GloFo.

Equipment companies are going to face some sort of increased sanctions. Anywhere from a total cutoff to strong tightening. Other customers, such as Taiwan, Korea and others will certainly not make up for any near term loss in China.

The only question at this point is how bad.

We think the stocks, even though they have been off have been holding up better than they should have given the current and expected state.

That will likely not be the case after quarterly reports that don’t talk about an end being in sight while potentially being forced to talk about the impact of yet to be know sanctions.

We would certainly lighten up ahead of the quarterly reports as the risk profile has increased beyond what is tolerable.

Companies with higher than average exposure to China obviously could see significant impact.

Its going to be a bumpy next few weeks no matter what…..

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

Micron Chip & Memory Down Cycle – It Ain’t Over Til it’s Over Maybe Longer and Deeper

Has U.S. already lost Chip war to China? Is Taiwan’s silicon shield a liability?

ASML-Strong Results & Guide Prove China Concerns Overblown-Chips Slow to Recover

Podcast EP186: The History and Design Impact of Glass Substrates with Intel’s Dr. Rahul Manepalli

Podcast EP186: The History and Design Impact of Glass Substrates with Intel’s Dr. Rahul Manepalli
by Daniel Nenni on 10-06-2023 at 10:00 am

Dan is joined by Dr. Rahul Manepalli. Rahul is an Intel Fellow and Sr. Director of Module Engineering in the Substrate Package Technology Development Organization. Rahul and his team are responsible for developing the next generation of materials, processes and equipment for Intel’s package substrate pathfinding and development efforts. He has been with Intel for over 23 years

Intel Ushers a New Era of Advanced Packaging with Glass Substrates

Rahul recounts the R&D efforts that Intel invested in glass substrates over the past decade. He details the challenges of bringing this material to the mainstream, with reliable handling being a major focus The performance, flexibility and scaling benefits of glass substrates are also discussed, along with a forward view of production deployment.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

Posted on

McKinsey & Company Shines a Light on Domain Specific Architectures

McKinsey & Company Shines a Light on Domain Specific Architectures
by Mike Gianfagna on 10-06-2023 at 8:00 am
Categories: AI, Events, Semiconductor Services, Silicon Catalyst

McKinsey & Company Shines a Light on the Impact of Domains Specific Architectures

When we hear McKinsey & Company, we may think of one of the “Big Three” management consultancies.  While that’s true, this firm has a reach and impact that goes far beyond management consulting. According to its website, the firm accelerates sustainable and inclusive growth.  While this is an inspirational statement, the purpose of the company really gets my attention – to help create positive, enduring change in the world. Silicon Catalyst felt the same way recently when they invited one of the partners from McKinsey to discuss the future of software and semiconductors. The comments made illustrate a solid understanding of the trends around us and a tendency to revolutionize results. Read on to see how McKinsey & Company shines a light on domain specific architectures.

The Event and the Speaker

 Silicon Catalyst hosted a networking event recently that focused on the future of compute. Presenting was Rutger Vrijen, Ph.D, a partner in McKinsey’s global Semiconductor and Advanced Electronics practice.

He serves semiconductor and other advanced-electronics clients on a range of topics, including growth strategy and transformation, cross-border M&A, pricing excellence, supply-chain performance diagnostics and transformation, as well as effective, efficient product development. With two patents and over 30 articles in globally leading scientific journals, Rutger had some insightful comments to share with the group.

The Discussion

Rutger Vrijen, Ph.D

Rutger began his talk with an overview of the forces that got us to domain specific architectures. Essentially, the slowing of transistor density scaling (Moore’s Law) and the acceleration of the energy cost (Dennard scaling).

While Moore’s Law is still quite important, process innovation is no longer enough to address the innovation requirements of advanced products. We must turn to architectural innovation and here is where domain specific architectures (DSAs) become relevant.

Rutger focused on the impact of DSAs across four main markets – HPC & AI, IoT, blockchain, and automotive. The impact is broader than this, but these markets exhibit some high-impact results from a workload-specific approach. Rutger reports that across these four domains, DSAs have an estimated 2026 market share of $89B, with HPC & AI leading the pack at $46B.

According to Rutger, the DSA movement has attracted around $18B in venture funding since 2012 and there are about 150 DSA startups today. The movement is real. Critical enablers for DSA innovators are becoming increasingly available, which will further accelerate changes.  These enablers include:

  • Increasing manufacturing leadership of foundries, providing universal access to leading manufacturing capabilities
  • A mature cloud market, delivering fast routes to customers and applications for chip startups that are integrated in cloud infrastructures
  • Increasing maturity of licensed and open-source hardware and software IP to democratize chip design and software stacks
  • Advanced semiconductor packaging and heterogeneous integration to interconnect DSAs with low latency and high bandwidth
  • Material innovations including paradigms beyond CMOS (e.g., photonic, neuromorphic)

Rutger went on to discuss the incredible impact DSAs and AI in general will have on design and manufacturing. The discussion was quite exciting. I’ll be sharing a link where you can get a lot of this detail in a moment. But first I want to convey one interesting use of AI that McKinsey was behind – the design of racing sailboats. 

It turns out this sport has some real challenges. The design of the boat is done over many months, with the need for a lot of simulation time. This requires actual humans to spend time in the simulator to debug the design. These are the same humans who are conducting press interviews and promotion for the event – a difficult balance. Something else I didn’t know – the actual race boat with final hydrofoil designs is physically available only a few weeks before the race. Talk about pressure.

McKinsey had a different idea. In 2021, they partnered with the New Zealand team to build a reinforcement learning approach to sailboat design. The software was able to adjust 14 different boat controls simultaneously, a task that typically takes three Olympic medalist sailors. This approach to extreme and continuous optimization paid off – New Zealand won the Americas Cup that year. This is another example of how McKinsey is quietly changing the world.

To Learn More

You can read the entire story about domain-specific architectures and the future of compute in the  McKinsey Insight piece here. McKinsey is also collaborating with the SEMI organization  for an event dedicated to DSAs and the future of compute. There is a who’s who lineup for this event. It will take place at SEMI headquarters in Milpitas, CA. Here are some of the presenters:

Startups

  • Cerebras – Dhiraj Mallick
  • SiMa – Gopal Hegde
  • Recogni – Marc Bolitho
  • Tenstorrent – Keith Witek, Aniket Saha
  • ai – Gavin Uberti

Investors

  • Silicon Catalyst – Pete Rodriguez
  • Cambium Capital – Bill Leszinski
  • ModularAI – Chris Lattner
  • Simon Segars

Ecosystem

  • Synopsys – Antonio Varas
  • Rescale – Joris Poort, Edward Hsu
  • GlobalFoundries – Jamie Schaeffer
  • TSMC – Paul Rousseau
  • LAM – David Fried
  • Advantest – Ira Leventhal
  • ASE – Calvin Cheung
  • Intel – Satish Surana

You can register for this event here. And that’s how McKinsey & Company shines a light on domain specific architectures.

Posted on

CEO Interview: Sanjeev Kumar – Co-Founder & Mentor of Logic Fruit Technologies

CEO Interview: Sanjeev Kumar – Co-Founder & Mentor of Logic Fruit Technologies
by Daniel Nenni on 10-06-2023 at 6:00 am
Categories: CEO Interviews

DSC01699

Sanjeev is a renowned technopreneur in the semiconductor industry. With more than 20+ years of experience, he is known for his enormous resilience and deep tech knowledge that sets him apart from others in the industry.

Sanjeev started his career as a hardware designer and then forayed into the FPGA domain due to his love for configurable hardware technologies. After acquiring a deep understanding of FPGA and implemented various high speed serial protocols controllers, he joined hands with Anil Nikhra (Co-Founder) to start Logic Fruit Technologies.

Prior to starting his entrepreneurial journey in 2009, Sanjeev was associated with Agilent Technologies as an FPGA Expert and NeoMagic as FPGA/Board R&D Lead. He is an EE graduate from IIT Kanpur and is passionate about sports fitness. He is an avid badminton player and cricketer.

Tell us about your company?

Logic Fruit Technologies (LFT) has completed 13 years of operations, having its niche in developing FPGA and CPU centric complex systems by utilizing organically growing Logic Fruit’s IP portfolio. Even though Logic Fruit develops a lot of RTL IPs, like PCIe, CXL, JESD204C, ARINC818 we are not an IP company but a system and solutions company.

We are preferred partners/vendors to key enterprise customers such as AMD, Intel, Keysight, Siemens, Lattice, Achronix and Indian Research PSUs like ISRO and DRDOs for investigation & feasibility study, and architecture development followed by complete development of the various systems & solutions.

Logic Fruit has developed and delivered 100+ Hardware & Software centric Solutions for diverse industries like Test and Measurement, Telecom, Aerospace & Defense, Semiconductor by using our capabilities and IPs in Hardware and Software Engineering.

The targeted market for Logic Fruit Technologies is US, Europe and India.

What problems are you solving?

Being a R&D focused product engineering company, our forte lies in providing customized solutions to our customers. LFT with its client-centric approach, aims to deliver tailored solutions aligned to customer’s specific challenges and objectives by utilizing the existing expertise and IPs.

Owing to confidentiality, we are not in a position to divulge any information regarding our ongoing projects. However, to showcase, we would like to tell you about ARINC 818 based single board computer, that has been developed with the Govt of India, under the TDFS schemes.

Logic Fruit takes pride in sharing that we are the first one to deliver the project under this scheme.

What application areas are your strongest?

Logic Fruit technologies has been primarily working on Aerospace & Defense, Test & Measurement, Semiconductors and Telecommunications. We are using our skill set around System Architecture, hardware design, RTL development, and SW design, to develop a complex heterogeneous to handle various kind of applications requiring real time high compute processing power.

What keeps your customers up at night?

Time to market, missing capability around FPGA technologies, a team who can deliver.

What does the competitive landscape look like and how do you differentiate?

Logic Fruit technologies is one of the leading product engineering companies with expertise in most advanced global technologies especially in FPGAs and Heterogeneous systems.

Our key differentiators are the expertise of working with FPGAs from over 20+ years and the over 50+ RTL IPs that we have built over the years, helps us to develop end-to-end solutions for our customers by reducing their overall development time and increase their confidence with our proven technologies in the end product.

What new features/technology are you working on?

Logic Fruit Technologies vision is to be a leader in Deep Technology Solutions by having various IPs around high-speed interfaces, programmable HW while delivering reliable, efficient, and scalable solutions to its global clients using our ever-growing IP portfolio and engineering capabilities.

We also look forward to being an effective contributor to Indian Government’s “Make in India” initiative specifically in the domain of Aerospace to Indianize complex systems.

How do customers normally engage with your company?

There are multiple channels how customers can engage with us e.g. online through website (https://www.logic-fruit.com) social media (LinkedIn, twitter), email (info@logic-fruit.com) and offline like referrals, in person events, Tech conferences etc. As we are in R&D profession so we have very strong NDAs in place and we keep our projects privacy at top priority and that is why we are able to work with defense and aerospace sector for more than a decade now.

Also Read:

CEO Interview: Stephen Rothrock of ATREG

CEO Interview: Dr. Tung-chieh Chen of Maxeda

CEO Interview: Koen Verhaege, CEO of Sofics

Posted on

proteanTecs On-Chip Monitoring and Deep Data Analytics System

proteanTecs On-Chip Monitoring and Deep Data Analytics System
by Kalar Rajendiran on 10-05-2023 at 10:00 am
Categories: Analytics, proteanTecs

On chip monitoring and analytics platform

State-of-the-art electronics demand high performance, low power consumption, small footprint and high reliability from their semiconductor products. While this imperative is true across many different market segments, it is critical for applications such as the automotive/autonomous driving and data centers. As electronic devices become more intricate and compact, the margin of error increases, necessitating innovative approaches to ensure optimal performance and longevity.

While traditional methods struggle to help deliver on this imperative, proteanTecs offers a comprehensive framework for enhancing product performance and reliability, through the integration deep data analytics. By combining data from specialty chip telemetry agents (monitoring IP) with machine learning (ML) algorithms, their solutions are deployed via cloud and embedded software to provide insights and visibility throughout the system lifecycle. These agents provide parametric design profiling, margin monitoring, power and reliability management, I/O channel health monitoring and in-field predictive monitoring. This groundbreaking solution is the proteanTecs On-Chip Monitoring and Deep Data Analytics System, and the company recently published a whitepaper on this subject matter. This whitepaper is an excellent read for everyone involved in the development of modern day applications that demand high performance and reliability. Following are some excerpts from that whitepaper.

On-Chip Monitoring and Analytics Platform

The success of the proteanTecs platform relies on two fundamental pillars, namely, comprehensive monitoring and data-driven analytics. By integrating these two elements into the chip design process, the company offers a holistic approach to optimization that covers the entire product lifecycle.

 

Ease of Implementing On-Chip Monitoring

The key is the platform’s ability to meticulously monitor critical chip parameters in real-time. This is achieved through a network of proprietary monitors, called agents, that are strategically placed within the chip architecture. These agents continuously gather data on parameters such as voltage, temperature, timing margins, and interconnect quality, all while the chip is in operation. This dynamic monitoring unveils a wealth of insights, unearthing vital information about a chip’s behavior under various workloads, conditions, and over its operational lifetime.

The hardware IP system from proteanTecs includes an extensive array of monitors for gathering data and a Full Chip Controller (FCC) that serves as the central hub. The FCC interfaces to the various monitors and relays the gathered data to the firmware (FW), edge software (SW) and the cloud platform via standard interfaces like JTAG, APB and I2C.

Ease of Incorporating Data-Driven Analytics

The data collected by the on-chip agents become the foundation for the second pillar of the proteanTecs platform which is deep data analytics. The platform boasts a sophisticated cloud-based analytics infrastructure that ingests, processes, and interprets the data. This complex ecosystem deploys advanced algorithms and machine learning techniques to dissect the intricate relationships between the monitored parameters and the chip’s performance, reliability, and power consumption.

The proteanTecs Software (SW) analytics platform operates in the cloud, acting as an interface to gather data from various sources like wafer probe, Automated Test Equipment (ATE) vendors, and the system during both productization and normal operation. The platform excels in Agent fusion and leverages Agent measurements to offer a comprehensive understanding of both the chip and the system.

Benefits from the proteanTecs Solution

During the New Product Introduction (NPI) phase, the platform’s Process Classification Agent (PCA) and Design Profiling Agent (DPA) collaborate to provide a comprehensive view of process characteristics and design sensitivity. This helps with process tuning, optimal voltage-frequency binning, and power management strategies.

As chips move from development to mass production, proteanTecs’ Timing Margin Agents (MA) come into play. These agents enable the accurate measurement of timing margins during functional operation, offering insights into actual system behavior that generic ring oscillators or critical path replicas cannot replicate. This leads to better understanding and control of the system’s performance, power consumption, and reliability.

Workload Agents (WLA) enable visibility into the application workloads and their impact on the hardware. They serve as a proxy for how much voltage and temperature stress the chip has been exposed to, during normal operation. This is important to determine the remaining useful life of a product and for efficient power and performance management.

The voltage droop sensor (VDS) and local voltage and thermal sensors (LVTS) enable real-time power and temperature management during the operational phase of a chip’s life. This not only maximizes performance but also extends the chip’s longevity by preventing excessive thermal degradation.

The solution’s impact extends into in-field monitoring and lifetime assessment, with embedded on-board software, in-chip monitoring and cloud analytics. By continuously monitoring key parameters, including those susceptible to performance degradation and latent defects, proteanTecs enables early detection of abnormal behavior that may lead to eventual failures. This preemptive capability is invaluable in critical applications, such as data centers and automotive systems, where reliability is paramount.

Summary

By integrating proteanTecs on-chip monitoring and deep data analytics solutions into their products, manufacturers can enhance their systems’ longevity, resilience, safety, and performance. The system offers unparalleled insights into chip behavior, performance optimization, and reliability enhancement. The end-to-end health monitoring fosters optimal reliability, performance, power efficiency, and cost-effectiveness across a broad spectrum of applications, ranging from automotive to data centers and beyond.

You can download the entire whitepaper from here. To learn more about proteanTecs technology and solutions, visit www.proteanTecs.com.

Also Read:

Predictive Maintenance in the Context of Automotive Functional Safety

Semico Research Quantifies the Business Impact of Deep Data Analytics, Concludes It Accelerates SoC TTM by Six Months

Maintaining Vehicles of the Future Using Deep Data Analytics