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CEO Interview: Dr. Tung-chieh Chen of Maxeda

CEO Interview: Dr. Tung-chieh Chen of Maxeda
by Daniel Nenni on 09-22-2023 at 6:00 am

Dr. Tung chieh Chen of MaxedaDr. Tung-chieh Chen has been serving as the CEO of Maxeda Technology since 2015. In 2021, at DAC, the largest EDA conference, Dr. Chen was honored with the Under-40 Innovators Award in recognition of his exceptional achievements and contributions to EDA development. He is the infrastructure designer of NTUplace, a circuit placer that has won in three top EDA contests: DAC, ICCAD, and ISPD.

In addition to his role at Maxeda, Dr. Chen has held positions as an R&D manager at SpringSoft and Synopsys. He has authored more than 30 EDA papers and holds 14 U.S. patents. Dr. Chen received his Ph.D. degree in Electrical Engineering and Computer Science (EECS) from National Taiwan University (NTU).

Tell us about Maxeda Technology
Maxeda Technology envisions pioneering AI-assisted EDA solutions for the optimization of next-generation chip design. Through close collaboration with partners, we develop validated floorplan and dataflow-analysis tools to support IC design engineers in overcoming design challenges, especially as the design complexity increases along with the macro quantities within the chip. Our clients include several global top 10 fabless companies and some well-known IC design service providers.

What keeps your customers up at night? What problems are you solving?
The semiconductor industry’s growth is driven by the chip requirements of AI/5G and high-performance computing applications, especially as Generative AI attracts increasing attention. Those chips contain millions of components, which results in designs becoming too complex to generate even by experienced engineers.

Therein lies the challenge: the optimized placement of these components is difficult given the huge number of possible placement states. Therefore more iterations are required to optimize the design and this is incredibly time-consuming.

As a consequence, a growing number of IC designers are now considering the incorporation of AI technology, particularly reinforcement learning, in their chip floorplan design process.

Even for a tech giant like Google, it is challenging to integrate Reinforcement Learning into the chip design flow. One reason is the need for more than 100,000 iterations to complete the learning process. Therefore it is an extremely time-consuming method that makes heavy demands on machine resources.

What is the solution Maxeda provided to address the problem and how do you differentiate?
A completely new approach is necessary to apply Reinforcement Learning to chip floorplan design. What is needed are ultra-fast placement and routing, ultra-fast rewards calculation, and a high correlation to final results. Maxeda is collaborating with MediaTek and NTU to develop the MaxPlace™ RL (Reinforcement Learning) Reward Platform to address these demands. Through expedited placement and its strong correlation with rewards, reinforcement learning has proven highly effective in optimizing chip performance, reducing the physical design process from months to just days. What sets this platform apart is its demonstrated performance in actual production.

Existing commercial place and route solutions, which take a completely different approach by aiming for precise placement and routing to meet chip tape-out criteria, are not well-suited for reinforcement learning due to their resource-intensive nature. Hence, no other vendor provides such an effective method for reward calculation.

Maxeda AI AssistedFigure 1: The MaxPlace™ RL Reward Platform optimizes chip floorplan design.

What are Maxeda’s upcoming plans?
As an EDA company with a vision to develop innovative solutions, Maxeda Technology continues to collaborate closely with partners to develop validated AI-assisted EDA solutions. In Q3 of 2023, we proudly released DesignPlan™, an SoC floorplan exploration tool designed to facilitate block outline and location exploration during the early stages of chip design. Furthermore, we are targeting the development of a completely new AI-assisted verification tool by the end of 2024.

Moreover, we are actively partnering with tier-one foundries to meet the evolving demands of advanced process nodes and navigate the challenges of the post-Moore era. We aim to expand our success from Taiwan to customers worldwide by leveraging this robust partner ecosystem.

Also Read:

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