SemiWiki – Page 110 – The Open Forum for Semiconductor Professionals

August 22, 2023August 22, 2023

Samtec Innovates a New Approach for High-Frequency Analog Signal Propagation

We are all familiar with the tradeoffs between copper and fiber for digital signal transmission. The short version is that fiber is flexible, like copper but supports higher data rates with less loss over longer distances. The bad news is that converting digital signals to light and back again isn’t a trivial process. These kinds of challenges also exist in the world of high-frequency analog transmission. For millimeter-wave applications, co-axial cable is the standard, just as copper is for digital. For higher frequencies and lower losses, waveguides are the step-up technology. This approach requires rigid structures that take up a lot of room and don’t route well. See the photo above. That is, until Samtec invented the first flexible waveguide cable. Read on to see how Samtec innovates a new approach for high-frequency analog signal propagation.

The Story of Waveguides

Waveguides

Thanks to Wikipedia, you can get a good overview of waveguide technology, its applications and its history here. As the name implies, these structures guide high-frequency signals through a defined, low-loss path as the signal propagates through air. The structures involved can be quite impressive, almost artistic in nature.

While these structures are eye-catching, they defy the mandate of every system design for a compact, efficient form factor.

Fortunately, the folks at Samtec have a nack for inventing new ways to propagate signals that is efficient, low loss and fits all design parameters. That core competency has allowed the company to re-invent the waveguide concept.

The Samtec Approach to Waveguides

What if waveguides could have a small profile and facilitate flexible routes with no loss of performance? This is exactly what Samtec is delivering, raising the bar for system design once again. Its next generation waveguide technology supports high frequency, low loss performance with a small form factor flexible cable. The product line appears to be a first for the industry.

Samtec waveguide

This new, high-frequency micro waveguide technology supports the demands of next generation millimeter wave systems. It uses a cable design allowing flexibility and a reduced size and supports frequencies up to 90 GHz, but with a loss performance greatly improved over coaxial cables.

As we see in the prior photos, higher frequencies often require the use of rigid, metallic waveguides. Samtec’s technology provides an alternative solution that is flexible, easier to use, and lower cost, while also maintaining the near-loss performance of a traditional rigid waveguide. This combination of features is unique and will open the door to new product designs.

Samtec recently demonstrated multiple applications of its new flexible waveguide technology at IMS 2023. You can check out this blog that describes the event. There is a 2.5-minute video in that blog that is worth watching. You will see the applications in action and get to see some impressive real-time statistics as well.

To Learn More

Samtec is focused on delivering world-class signal integrity. You can learn more about this corporate obsession here. The new, flexible waveguide products are another way Samtec delivers on this promise. I can’t wait to see what new products are inspired by this capability.

Over the next few weeks Samtec will deliver a lot more information about this new product line. Things like:

Series information: WF12 (E-band waveguide), WGBA (adaptor), WF15 (V-band waveguide)
Product overview
Catalog page
Prints
Videos
And more

If you’re interested in learning more, bookmark this page and check on it from time to time over the next few weeks. You won’t be disappointed. And that’s how Samtec innovates a new approach for high-frequency analog signal propagation.

Also Read:

Signal Integrity 101: Fundamentals for Professional Engineers

PCI-SIG DevCon and Where Samtec Fits

Samtec Lights Up MemCon

Samtec Dominates DesignCon (Again)

August 22, 2023December 27, 2023

Bluetooth Based Positioning, More Accurate, More Reliable, Safer

Bluetooth Based Positioning, More Accurate, More Reliable, Safer
by Bernard Murphy on 08-22-2023 at 6:00 am
Categories: Automotive, Ceva, IP

Using Bluetooth for positioning is a topic I have touched on before, for location services, keyless entry, and asset tracking among other applications. Earlier implementations depended on measures of received signal strength and angle-of-arrival / angle-of-departure, but these have limited accuracy in environments with complex reflection paths such as a parking lot or indoor environments. They also have limited security, driving implementations paired with UWB for keyless entry though not necessarily fixing security problems in the Bluetooth path. The Bluetooth SIG felt they could do more with BLE and continues to move towards a better solution.

Channel sounding for high accuracy secure positioning

Channel sounding in the cellular world is a technique commonly thought of for characterizing channels for MIMO platforms. It was also popular in early radio-based navigation systems. These methods leverage round-trip signaling across multiple channels, using phase difference or time of flight to minimize multi-path effects or to increase positioning accuracy.

The Bluetooth SIG is working on standardized channel sounding in an upcoming release, allowing solution builders to leverage the ubiquity and low power advantages of BLE to further extend value to multiple applications. By combining estimates across multiple channels, channel sounding can achieve position accuracies down to tens of centimeters.

This capability can offer significant improvements over current keyless entry systems for cars both in accuracy and in reliability in congested environments such as a parking lot. Even more important, improved security in Bluetooth channel sounding will defeat relay attacks which have been demonstrated quite recently. Such attacks allow an attacker to trick a victim car into opening locks.

Channel sounding will also be valuable in asset tracking, say in a warehouse where small packages may still be difficult to locate without sufficient positioning accuracy. The same capability could also become very popular for indoor wayfinding, for example in large malls or other buildings.

Opportunity

Market analysts forecast that over 500 million Bluetooth-based low power positioning devices will ship annually by 2030, based on a CAGR of 28.5% from 2022 to 2030. The keyless entry subset of this market also demands the high security offered by this planned release to defeat distance-spoofing and relay attacks and is estimated to reach $5.5B by 2032, at a CAGR of 12.8%. Meanwhile the asset tracking IoT market wants precision positioning to optimize warehouse operations. This market is expected to grow to $8.5B by 2030.

CEVA and channel sounding

CEVA has been a well-established and respected supplier of embedded Bluetooth technologies over the last 20 years through their RivieraWaves family supporting both classic and LE profiles. Since the official channel sounding option is still in discussion in the Bluetooth SIG, CEVA decided to get ready early with a release of their own, aiming to track the anticipated standard as closely as possible. Not a bad idea. That option should allow builders to refine product ideas, ensuring they will be ready when the standard is ratified and solutions are qualified.

You can read the press release HERE and learn more about CEVA’s Bluetooth connectivity solutions.

August 21, 2023September 1, 2024

How Intel, Samsung and TSMC are Changing the World

How Intel, Samsung and TSMC are Changing the World
by Mike Gianfagna on 08-21-2023 at 10:00 am
Categories: Analytics, Foundries, Intel Foundry, Samsung Foundry, TSMC
3 Comments

Given the changes in the music business, the term “Rock Star” doesn’t really have any relevance to music or its performers anymore. Instead, we use the term to describe leaders, innovators and generally people or organizations of great significance. In the world of semiconductors, the designers of advanced chips were the rock stars for a long time. Those who put those chips in packages were regarded as the clean-up crew. A roadie for the rock star at best.

Thanks to the coming revolution of multi-die design, packaging is now a fundamental technology driver and advanced packaging engineers are now the rock stars. These trends promise to change the semiconductor industry and the world. SemiWiki recently received some compelling data on this topic. The sources of the data are just as interesting as the data itself. Read on to understand how Intel, Samsung and TSMC are changing the world.

The Data, Who is Watching What

This all began with an email from The Bulleit Group entitled Intel Stock Down, Why TSMC Might Be Responsible. The Bulleit Group, in its own words, was founded in 2012 by Kyle Arteaga and Alex Hunter over a glass of Bulleit Bourbon (no relation). Once I read that, I had to learn more. This is a tech agency with a twist – a singular focus on what’s next, how to get there and what it means. The company’s rotating home page graphic illuminates its mission.

We tell stories about:

the future
frontier technology
sci-fi becoming reality
a better world
challenging the status quo
mavericks
the nexus of technology and culture

The punch line is:

Throughout the past ten years, technology has changed everything about the way we live. We’re focused on the next ten.

I found it gratifying that a forward-looking, award-winning organization like this was interested in semiconductor packaging. But this isn’t the end of the story. The Bulleit Group was writing to share information it had received from LexisNexis, another catchy name I hadn’t heard of.

LexisNexis is an intellectual property solutions provider. The company’s tagline is Bringing Clarity to Innovation. In its own words, we are proud to directly support and serve (innovators) in their endeavors to better humankind. Another award-winning and unique organization with a global perspective. And their team is focused on semiconductor packaging. Life is good.

The Data, What it Means

Let’s look at what LexisNexis is saying. Since the organization focuses on IP, a patent analysis is in its wheelhouse. This analysis was based on 37,779 patent families active on 07/20/2023. That’s a lot of data to analyze. The results are quite interesting. Below are the top ten patent producers.

Top ten patent producers

TSMC, Samsung and Intel are clearly in the lead. The Bulleit Group summarizes this data as follows:

LexisNexis discusses the different approaches of semiconductor companies regarding advanced packaging, with Intel focusing on high-performance computing, for example, Samsung targets high-volume assembly, and TSMC aims to capture a wide range of trends from low-cost to high-performance computing. In addition, these topics are not only important to the manufacturers above, but these topics are also relevant to fabless companies such as AMD, Apple, Broadcom, Nvidia, Qualcomm, etc., particularly in the continuing demand for AI-enabled technologies.

Reuters covered these trends in a recently published story. The article commented, “Advanced packaging is crucial for improving semiconductor designs as it becomes more difficult to pack more transistors onto a single piece of silicon. Packaging technology enabled the industry to stitch together several chips called “chiplets” – either stacked or adjacent to one another – within the same container.” Once again, the mainstream media has taken notice of significant, world-changing trends in semiconductors. Honestly, this feels quite good.

“They seem to be the ones that pulled the field forward, and set the technology standard,” said LexisNexis PatentSight Managing Director Marco Richter in an interview, referring to TSMC, Samsung and Intel.

Additional insights from LexisNexis illustrate the substantial growth of the advanced packaging sector. See below. Back to that rock star comment.

Advanced packaging trends

To Learn More

If you’re interested in digging deeper, here are two reports from LexisNexis that may be of interest:

Innovation Momentum 2023: The Global Top 100

Exploring the Global Sustainable Innovation Landscape: The Top 100 Companies and Beyond

The second report dives into the links between sustainability and technology innovation. And that’s how Intel, Samsung and TSMC are changing the world.

Also Read:

Intel Enables the Multi-Die Revolution with Packaging Innovation

TSMC Redefines Foundry to Enable Next-Generation Products

VLSI Symposium – Intel PowerVia Technology

TSMC Doubles Down on Semiconductor Packaging!

August 21, 2023August 21, 2023

Enhanced Stochastic Imaging in High-NA EUV Lithography

Enhanced Stochastic Imaging in High-NA EUV Lithography
by Fred Chen on 08-21-2023 at 8:00 am
Categories: Lithography

High-NA EUV lithography is the anticipated new lithography technology to be introduced for the 2nm node. Essentially, it replaces the 0.33 numerical aperture of current EUV systems with a higher 0.55 numerical aperture (NA). This allows the projection of smaller spot sizes and smaller pitches, roughly 60% smaller compared to 0.33 NA systems. However, the depth of focus of the projected image is limited, due to being inversely proportional to the square of numerical aperture and directly proportional to the square of resolution. A wider numerical aperture leads to a wider range of illumination angles. This, in turn, leads to a larger phase difference from defocus among different spatial frequency components of the image, such as diffraction orders for an array.

Figure 1. Allowed illumination angles for 28 nm pitch square array, within the first quadrant of the 0.55 NA pupil. The number labels indicate the maximum phase range (in degrees) among the four beams (diffraction orders) making up the image, for a 30 nm defocus. The blue trapezoid outline indicates the zone for minimum 20% pupil fill (5% in one quadrant) to prevent light absorption within the illuminator.

Figure 1 shows the range of phases among the four diffraction orders of a 28 nm square pitch pattern for a 0.55 NA EUV system. The phase range already exceeds 90 degrees, which leads to a maximal intensity change for at least one of the four orders. 30 nm defocus is prohibitive with 20% pupil fill. Resist thickness is therefore expected to be limited to on the order of 20 nm. This leads to an expected absorption of ~10% in organic resists with absorption coefficients of 5/um [1,2]. 0.33 NA systems use resist thicknesses at least twice as thick, allowing absorption of at least ~20%. Thus, the 0.55 NA systems have higher risk of stochastic effects in imaging.

Figure 2. 14 nm dense (28 nm pitch) spot formed as a positive tone darkfield image, assuming 10 mJ/cm2 (absorbed over the whole pitch, >100 mJ/cm2 incident on 20 nm thickness). The nominal image is on the left, while the actual stochastic image is on the right. The numbers indicate the photons absorbed per 0.5 nm x 0.5 nm pixel.

For a 14 nm half-pitch spot in the organic resist case (Figure 2), the absorption outline is rough with very uncertain edge placement, while the interior has numerous areas where no absorption occurs.

Metal oxide resists have absorption coefficients on the order of 20/um (33% absorption in 20 nm thickness) [1,2], so they can provide more photon absorption. However, they are negative tone. That means a bright spot forms a pillar, while a dark spot forms a hole.

Figure 3 14 nm dense (28 nm pitch) spot formed as a negative tone brightfield image, assuming an absorbed dose of 35 mJ/cm2 (>100 mJ/cm2 incident on 20 nm thickness). The nominal image is on the left, while the actual stochastic image is on the right. The numbers indicate the photons absorbed per 0.5 nm x 0.5 nm pixel.

Even for the higher absorbing metal oxide resist (Figure 3), the outline is still very rough and there even appear to be nano-extensions of absorption toward adjacent spots, further blurring the edge. The reason is the lower edge contrast along the horizontal and vertical directions (for 28 nm square array pitch) means stochastic dose fluctuations have a larger opportunity to cross the printing threshold.

0.55 NA EUV imaging therefore requires even higher absorption than 0.33 NA EUV imaging, and this means much more absorptive resists than have already been studied. One other factor not yet considered is electron blur, as increased absorption also means more electrons moving around in the resist. This needs to be covered in a future study.

References

[1] R. Fallica et al., Proc. SPIE 10143, 101430A (2017).

[2] D. De Simone et al., Proc. SPIE 10143, 101430R (2017).

This article first appeared in LinkedIn Pulse: Enhanced Stochastic Imaging in High-NA EUV Lithography

Also Read:

Application-Specific Lithography: Via Separation for 5nm and Beyond

ASML Update SEMICON West 2023

NILS Enhancement with Higher Transmission Phase-Shift Masks

August 21, 2023August 21, 2023

How Philips Saved TSMC

How Philips Saved TSMC
by Daniel Nenni on 08-21-2023 at 6:00 am
Categories: Foundries, TSMC

TSMC and Philips have deep historical ties. In fact, TSMC may not have existed without Philips. In the 1980s TSMC was established as a joint venture with Philips Electronics, the government of Taiwan, and other private investors. Several semiconductor companies were approached by Morris Chang for funding including semiconductor giants Intel and Texas Instruments but neither chose to participate. Both Intel and TI are now TSMC customers so it came full circle.

Only Philips was willing to sign a joint venture contract with Taiwan to put up $58 million in exchange for a 27.5 percent stake in TSMC. The Taiwanese government provided another 48 percent of the startup capital for TSMC and the rest of the capital was raised from private investors. The government asked several of the island’s wealthiest families who owned firms that specialized in plastics, textiles, and chemicals, to put up the money. TSMC was really a Taiwanese enterprise rather than a normal start-up semiconductor company.

It wasn’t just the money, Philips also played a crucial role in the early days of TSMC by transferring semiconductor manufacturing technology, IP and patents to the newly-formed company and working closely as an investor, partner, and customer. Philips really was the first semiconductor company to go fab-light due to the rising costs of building and operating fabs.

Even though they had a minority stake, Philips had quite a bit of influence and even installed the first TSMC CEO James E. Dykes, who had previously worked for Philips North America. I will write more about James in the next installment.

However, over time, Philips reduced its stake in TSMC, and the two companies evolved in different directions. Philips shifted its primary focus to health technology while TSMC concentrated on becoming the most successful pure-play foundry in history, absolutely. The other semiconductor powerhouse Philips has historical ties to is ASML (ASML was a spinout of Philips Labs) but that is another story in itself.

Here is some background on Philips from ChatGPT-4:

“Founded in 1891 by Gerard Philips and his father Frederik in Eindhoven, the Netherlands, Philips, or Koninklijke Philips N.V. (Royal Philips), is a leading multinational conglomerate known for its diversified technology solutions. Initially starting as a company manufacturing incandescent lamps and other electrical products, Philips expanded over the decades into various sectors.

Here’s a brief overview of Philips’ trajectory over the years:

Early Days (1891 – 1920s): The company initially focused on producing carbon-filament lamps. They soon became one of the largest producers in Europe.

Radio and Electronics (1920s – 1940s): Philips entered the radio market in the 1920s. By the 1930s, they were one of the largest radio manufacturers in the world. They also started producing X-ray and radio technology during this period.

Post-war Era (1940s – 1960s): After World War II, Philips was involved in the revival of the Stirling engine. They also diversified into products like television sets and shavers during this period.

Electronics Expansion (1970s – 1990s): Philips expanded further into electronics, producing items like cassette tapes, CD players, and other home electronics. The company co-developed the Compact Disc (CD) with Sony.

2000s and beyond: In the 21st century, Philips started streamlining its operations to focus on health technology and personal health solutions. They sold off or spun off many non-core divisions, such as their semiconductor division (NXP Semiconductors) and their lighting division (Signify). The company’s primary focus has been on healthcare, diagnostic imaging, patient monitoring, health informatics, and personal care.

Throughout its history, Philips has been known for innovation and has been responsible for a number of significant technological advancements. The company operates globally and continues to be a major player in the fields it is active in.“

The Dutch had an even deeper connection to Taiwan dating back hundreds of years. Here is a 10 minute history video that covers it nicely and is well worth watching:

Next up: TSMC’s first CEO James E. Dykes and the Taiwan Semiconductor Outlook (May 1988).

Also Read:

How Taiwan Saved the Semiconductor Industry

Morris Chang’s Journey to Taiwan and TSMC

EP177: The Certus Approach to Meeting the Challenges of I/O and ESD with Stephen Fairbanks

EP177: The Certus Approach to Meeting the Challenges of I/O and ESD with Stephen Fairbanks
by Daniel Nenni on 08-18-2023 at 10:00 am

Dan is joined by Stephen Fairbanks, CEO of Certus Semiconductor. Stephen is an ESD pioneer with over 30 years of experience starting with his time at Intel, SRF Technologies, and now Certus Semiconductor.

Stephen describes the varied challenges of ESD andI/O library design presented by today’s technologies and design styles. He outlines what Certus Semiconductor is doing to address these challenges with unique design approaches and deep domain expertise.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

August 18, 2023January 10, 2024

CEO Interview: Anna Fontanelli of MZ Technologies

CEO Interview: Anna Fontanelli of MZ Technologies
by Daniel Nenni on 08-18-2023 at 6:00 am
Categories: Chiplet, EDA, MZ Technologies

Anna has more than 25 years of expertise in managing complex R&D organizations and programs, giving birth to a number of innovative EDA technologies. She has pioneered the study and development of several generations of IC and package co-design environments and has held senior positions at leading semiconductor and EDA company including STMicroelectronics and Mentor Graphics.

Tell us about MZ Technologies

MZ Technologies is the marketing brand of Monozukuri S.p.A. The parent opened for business in Rome, Italy with an initial capital of € 3.5 million in R&D. Since we first opened our doors, our singular focus has been shrinking the time-to-design of complex chiplet and package co-design challenges. Our mission is to envision, develop and deliver software automated tools and technology that transform the next generation of vertically stacked, modularly packaged integrated circuits designs into commercial successes through superior time-to-market and yield-to-volume efficiencies.

I’m happy to say that we’re making good progress toward achieving the objective we set eight years ago with the introduction of the industry’s first, fully integrated IC/Packing Co-Design EDA tool. To date, we’ve proven the validity of our technology and successfully generated revenue in both Asia and Europe, so now it makes sense for us to bring our expertise to North America.

What problems are you solving?

Great question, and the answer goes directly to our vision. Simply put, one of the major challenges our customers face is the miniaturization of microelectronics devices. We believe that how society interacts with itself, with technology, and the future will be molded by the Moore’s Law spirit of exponential functional innovation.

To that end, we take on one of the industry’s thorniest problems: Creating the technology design nexus that transforms visions of the future into tomorrow’s innovative IC reality.

What application areas are your strongest?

MZ Technologies delivers innovative, ground-breaking EDA chiplet and package co-design software and methodologies for 2.5D and 3D integrated IC architectures. Our tool, GENIO™, redefines the co-design of next generation heterogeneous microelectronic systems by dramatically improving the automation of integrated silicon and package EDA flows through three-dimensional interconnect optimization.

What keeps your customers up at night?

Let me see if I can explain it this way.

The adoption of 3D stacked silicon architecture demands semiconductor chiplets interconnected with large number (thousands) of I/Os. This translates into higher complexity during the layout engineering phase of a system design, which already accounts for 1/3 of the process from design start to mask layer sign-off. Additionally, the traditional design approach is based on several long and costly design cycles followed by iterative design re-spins before coming to convergence on final product/result. This approach, due to time-to-market limitation, forces the designer to stop at a “good-enough” and usually sub-optimal solution.

Quite a conundrum, no? Well, where GENIO^TM fits in is that as a holistic design environment spanning across the complete 3D design eco-system, it provides a co-design platform that enables a revolutionary design approach not only putting in communication different design environments (such as IC, Package and PCB) but also empowering the integration with physical implementation tools – physical routers in both space- as well as analysis tools -signal and power integrity and thermal analysis- for physical-aware and simulation-aware 3D system interconnect optimization.

What does the competitive landscape look like and how does MZ Technologies differentiate?

There really isn’t anything like GENIO today, because it was built from the ground-up. Most of the tools that attempt to do what GENIO does are what we refer to as “bolt-ons.” In other words, capabilities designed for one function are literally mashed on to another set of capabilities in hopes of overcoming a new set of design challenges.

GENIO, on the other hand, was design and built from the ground-up. Its system optimization from a unique dedicate cockpit that supports a 3D-aware cross-hierarchical pathfinding algorithm and a rule-based methodology that delivers single-step interconnect optimization throughout the entire 3D system hierarchy.

It’s a chiplet-based system-level architectural exploration that delivers “concept” design phases before physical implementation starts for I/O planning an interconnect optimization that creates and manages the physical relationship and hierarchy between components. And, it uses “what if” analysis and early feasibility studies avoid “dead-end” architecture.

This novel approach creates never-before-seen levels of IC system integration that shorten the

design cycle by two orders of magnitude; drive faster time-to-manufacturing, improve yields, and streamline the entire IC eco-system to enable function- intensive IC-designs that will be the

backbone for the most advanced next-generation integrated circuits. As a result, the optimal system configuration is finally in-reach. It will reduce the overall system design cost dramatically, bringing the “missing piece of the EDA puzzle” needed to complete the 3D-IC design flow.

What new capabilities are you working on?

Today, the commercially available version of GENIO is back-end oriented. What I mean by that is that it is integrated with and has been validated with physical implementation tools for chiplet-based 3D-stack floor planning that accommodates multiple IP libraries.

The next generation of GENIO will better serve customer requirements by extending the tool’s front-end capabilities for simulation-aware system interconnect optimization and early-on system analysis. The early-on system analysis capability will be very robust. It will include state-of-the-art TSV models with R/C electrical performance and mechanical/thermal behavior. It will also provide thermal modeling based on power dissipation map and TSVs contribution. Other features will include V&T monitors placement according to identified thermal hotspots and integration with a Hardware-In-the-Loop emulation platform.

How do customers normally engage with MZ Technologies?

Right now, we’re engaging with companies through our representation in Europe and Israel while we open up representation here in North America. We usually initiate every engagement with an initial presentation and demo of GENIO. We then move to installing a demon on the customer premises for non-production purposes. Alternatively, we can run proof-of-concept on customer test cases at our facility. The final step is annual subscription, full GENIO installation that includes support, maintenance and wiki-like users’ manual and tutorials.

Also Read:

CEO Interview: Harry Peterson of Siloxit

Breker’s Maheen Hamid Believes Shared Vision Unifying Factor for Business Success

CEO Interview: Rob Gwynne of QPT

August 17, 2023August 17, 2023

Sirius Wireless Partners with S2C on Wi-Fi6/BT RF IP Verification System for Finer Chip Design

Sirius Wireless Partners with S2C on Wi-Fi6/BT RF IP Verification System for Finer Chip Design
by Daniel Nenni on 08-17-2023 at 10:00 am
Categories: EDA, Prototyping, S2C EDA

Sirius Wireless, a provider of RF IP solutions, collaborated with FPGA prototyping solutions expert S2C to develop its Wi-Fi6/BT RF IP Verification System, aiming to improve work efficiency and reduce time-to-market for their clients.

The emergence of Wi-Fi6, a wireless connection technology (WCT), has unleashed unexpected potential, particularly in the IoT and intelligent hardware markets. Compared to Wi-Fi5, Wi-Fi6 enables 40% faster data transmission speeds, increased device connectivity, and improved battery life, making it widely adopted in IoT devices. Due to the specialized RF IP technology behind Wi-Fi6, only a few companies can provide such technology with Sirius being one of them.

Leveraging S2C Prodigy S7-9P Logic System, Sirius Wireless designed the Wi-Fi6/BT RF IP Verification System with AD/DA and the RF front-end AFE as separate modules. The company then used Prodigy Prototype Ready IP which are ready-to-use daughter cards and accessories from S2C, to interface with digital MAC. This design approach reduces the complexity of verification design by allowing the modules to be individually debugged. In addition, the system can serve as a demonstration platform prior to tape-out to showcase the various RF performance indicators, including throughput, reception sensitivity, and EVM.

S2C FPGA prototyping solutions greatly benefit customers in accelerating their time-to-market by shortening the entire chip verification cycle. S2C customers can conduct end-to-end verification easily by leveraging the abundant I/O connectors on the daughter boards. An example of such benefits is Sirius’s development of its IP verification system. With this system, one of Sirius’s customers on short-range wireless chip designs spent only two months to complete the pre-silicon hardware performance analysis and performance comparison test. The company thus saves over 30% in its production verification time and its customers’ product introduction cycle.

“S2C has more than 20 years of experience in the market.” said Zhu Songde, VP Sales of Sirius Wireless, “Their prototyping solutions are widely recognized around the world. With S2C’s complete prototype tool chain, we can speed up the deployment of prototyping environments and improve verification efficiency.”

S2C is committed to building an ecosystem with their partners. “We realize that a thriving ecosystem is crucial to market expansion.” said Ying Chen, VP of Sales & Marketing at S2C, “We are working with our partners to provide better services for our customers in the chip design industry. Our partnership with Sirius Wireless is a successful story of that.”

About Sirius Wireless
Headquartered in Singapore, Sirius Wireless was registered and established in 2018. The company has professional and outstanding R&D staff with more than 15 years of working experience in Wi-Fi, Bluetooth RF/ASIC/SW/HW.

About S2C
S2C is a leading global supplier of FPGA prototyping solutions for today’s innovative SoC and ASIC designs, now with the second largest share of the global prototyping market. S2C has been successfully delivering rapid SoC prototyping solutions since 2003. With over 600 customers, including 6 of the world’s top 15 semiconductor companies, our world-class engineering team and customer-centric sales team are experts at addressing our customer’s SoC and ASIC verification needs. S2C has offices and sales representatives in the US, Europe, mainland China, Hong Kong, Korea, and Japan.

Also Read:

S2C Accelerates Development Timeline of Bluetooth LE Audio SoC

S2C Helps Client to Achieve High-Performance Secure GPU Chip Verification

Ask Not How FPGA Prototyping Differs From Emulation – Ask How FPGA Prototyping and Emulation Can Benefit You

August 17, 2023August 22, 2023

How Do You Future-Proof Security?

How Do You Future-Proof Security?
by Bernard Murphy on 08-17-2023 at 6:00 am
Categories: Automotive, Secure-IC, Security

If you are designing electronics to go into a satellite or a military drone, it better have a useful lifetime of 15-20 years or more. Ditto for the grid or other critical infrastructure, your car, medical devices, anything where we demand absolute reliability. Reliability also requires countermeasures against hacking by anyone from a teenage malcontent to a nation-state actor with unbounded resources.

Hacks and defenses are a moving target, demanding forward planning and agility in how a system can respond to new threats and defenses. A purely software-based security system would provide maximum flexibility but is no longer a credible option – software is easier to hack than hardware. Hardware options such as a root of trust provide better defense but are not arbitrarily flexible. A combination of hardware and software would be ideal, but the hardware must be optimized to support evolving defenses over that extended life. How is this possible?

We can’t be certain what future attacks might look like, but we can tap into the collective wisdom of those agencies and organizations most sensitive to security risks as a pretty good proxy. We ourselves also need to become more comfortable with anticipating risks we cannot yet see. As geopolitical tensions build and attack surfaces grow thanks to automation and concentrated targets of opportunity in cloud and communications infrastructure, a blinkered obsession over short-term priorities may be a fast path to obsolescence following the next big hack.

Raising the bar in security

While I’m not an avid fan of the hype around quantum computing, an organization with unlimited funds should eventually be able to build a system capable of cracking a production application based on say integer factorization. Cloud access would then herald open season on hacking pretty much anything.

Fortunately, there are algorithms that are resistant to quantum attacks (here is an easy intro to lattice-based ideas as one example). The Department of Homeland Security has documented a timeline for adoption of NIST approved standards for post-quantum cryptography (PQC), anticipating release of a “cryptographically relevant quantum computer” by 2030.

The cryptography engine forms the heart of any root of trust, in turn the heart of hardware security, supporting secure boot, anti-tampering, side-channel hardening, key isolation and more. Concrete evidence of the readiness of such an engine for long-term deployment in demanding security environments would then be its adoption in military grade applications operating under harsh environments (satellites for example). In automotive applications, compliance with the relatively recent ISO 21434 standard is a new hurdle to clear. Together, naturally, with ASIL-D compliance since security among all electronic functions must comply with the highest standards of safety.

Authentication, the ground truth for communication between the cloud and a device, depends on a strong PUF which should be certified for ISO/IEC 20897 compliance, a set of standards on how to assess PUF quality over an extended life cycle.

In addition, any credible long term solution must include a secure communication solution – secure in cloud support, in the communication channel and in the chip – for provisioning, updates, monitoring and intrusion detection.

Futureproofing is probably not going to be possible through piecemeal incremental extensions to an existing security strategy. But that shouldn’t be surprising; you wouldn’t expect a security architecture expected to meet a 15-year lifetime to require less than a major step forward. Secure-IC appears to worth investigating as a potential provider.

About Secure-IC

Secure-IC is a pure-play security company with focus on IP, software, and services. They are based in Cesson-Sévigné (France), with offices in Paris and subsidiaries in Singapore, Tokyo, San Francisco, Shanghai, Taiwan, and Belgium. They have over 130 staff, a billion IP shipped and over 200 customers worldwide. They spun out of Paris Telecom University in 2010 with a strong and continuing commitment to research in security, as evidenced in papers published regularly in multiple conferences and journals.

Secure-IC are involved in a number of standards organizations and are actively familiar with standards such as Common Criteria (CC), FIPS140-3, ISO21434, OSCCA (China), and IEC62443. They also actively involved in client security planning and development through security evaluations and services in support of security compliance and certification.

As usual given the sensitivity of the security domain they are reluctant to discuss customers. However, from my discussion with Benjamin Lecocq (head of sales for the US) and poking around on their website I was able to infer that they are already deployed in satellites (I’m guessing for defense/intelligence applications), they have a DARPA partnership, and they seem to have quite widespread adoption among automotive Tier1/2 and OEMs. They were also listed in the Financial Times survey of fastest growing companies in Europe based on highest CAGR for 2017-2022.

A company you should include on your shortlist of security partners, I would think. You can learn more from their website.

August 16, 2023January 17, 2024

LIVE WEBINAR: Accelerating Compute-Bound Algorithms with Andes Custom Extensions (ACE) and Flex Logix Embedded FPGA Array

LIVE WEBINAR: Accelerating Compute-Bound Algorithms with Andes Custom Extensions (ACE) and Flex Logix Embedded FPGA Array
by Daniel Nenni on 08-16-2023 at 2:00 pm
Categories: Andes Technology, eFPGA, Events, Flex Logix, IP, RISC-V

RISC-V have great adoption and momentum. One of the key benefits of RISC-V is the ability for SoC designers to extend its instruction sets to accelerate specific algorithms. Andes’ ACE (Andes Custom Extensions) allow customers to quickly create, prototype, validate and ultimately implement custom memories, dedicated ports to accelerators and memories. Andes automates many of these tasks with its COPILOT (Custom-OPtimized Instruction deveLOpment Tools). COPILOT is an all-in-one design tool to implement custom extensions and instructions in easy to use simple language, automatically enables simulations with these extensions and finally, creating self-verification methodology to ensure the extensions are operating correctly.

SEE REPLAY HERE

However, there are two challenges to adding custom extensions to RISC-V processors that are not usually considered. One, these extensions do take gates that are designed for specific acceleration. Two, you cannot add more custom extensions and instructions after you fabricate the chip to expand target applications and extend the useful life of the chips.

Flex-Logix’s eFPGA capability brings a new dimension to solving these challenges to Custom Extension. Imagine the old toys we played with “Etch a Sketch” that gave you a blank slate to create art over and over again. Flex Logix’s solutions gives you the blank slate of gates that can be used over and over again with your SOC. By using Flex-Logix’s reprogrammable fabric, these instructions can be “programmed” as needed, and those gates can be reused for multiple instructions. Even better, one can create instructions and extensions AFTER the SoC is fabricated to target new software workloads for different applications or improve performance and power with new instructions after the chip is deployed in the field. This is the ultimate software update that can extend the life of the SOC’s.

Andes and Flex-Logix are working together to create the ultimate Etch a Sketch for the Engineers and Architects. And we hope to make it as easy as our childhood toys to unleash our creativity in order to accelerate processing while lowering the cost of Area and Power in order the next generation of SOCs tailored for embedded computing in IOT and Machine learning.

SEE REPLAY HERE

Over a series of Webinars for rest of 2023, Andes and Flex will present our solutions for creating and fielding Andes Custom Extensions. And we are working hard to bring tighter integration of our two companies’ technologies in order to allow the SoC Architects to imagine solutions that are fully optimized and truly extendable, even after the Chips have been created.

About Flex Logix
Flex Logix is a reconfigurable computing company providing leading edge eFPGA and AI Inference technologies for semiconductor and systems companies. Flex Logix eFPGA enables volume FPGA users to integrate the FPGA into their companion SoC, resulting in a 5-10x reduction in the cost and power of the FPGA and increasing compute density which is critical for communications, networking, data centers, microcontrollers and others. Its scalable AI inference is the most efficient, providing much higher inference throughput per square millimeter and per watt. Flex Logix supports process nodes from 180nm to 7nm, with 5nm in development; and can support other nodes on short notice. Flex Logix is headquartered in Mountain View, California and has an office in Austin, Texas. For more information, visit https://flex-logix.com.

About Andes Technology
Eighteen years in business and a Founding Premier member of RISC-V International, Andes is a publicly-listed company (TWSE: 6533; SIN: US03420C2089; ISIN: US03420C1099) , a leading supplier of high-performance/ low-power 32/64-bit embedded processor IP solutions, and the driving force in taking RISC-V mainstream. Its V5 RISC-V CPU families range from tiny 32-bit cores to advanced 64-bit Out-of-Order processors with DSP, FPU, Vector, Linux, superscalar, with processor integrating vector processor and/or multi/many-core capabilities. By the end of 2022, the cumulative volume of Andes-Embedded™ SoCs has surpassed 12 billion. For more information, please visit https://www.andestech.com. Follow Andes on LinkedIn , Twitter, Bilibili and YouTube!

Also Read:

CEO Interview: Frankwell Lin, Chairman and CEO of Andes Technology

Reconfigurable DSP and AI IP arrives in next-gen InferX

eFPGA goes back to basics for low-power programmable logic