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Alchip is Paving the Way to Future 3D Design Innovation

Alchip is Paving the Way to Future 3D Design Innovation
by Mike Gianfagna on 11-19-2024 at 6:00 am
Categories: 3D IC, Alchip, Events, Semiconductor Services

Alchip is Paving the Way to Future 3D Design Innovation

At the recent TSMC OIP Ecosystem Forum in Santa Clara, there was an important presentation that laid the groundwork for a great deal of future innovation. Alchip and its IP and EDA partner Synopsys presented Efficient 3D Chiplet Stacking Using TSMC SoIC. The concept of 3D, chiplet-based design certainly isn’t new. SemiWiki maintains dedicated forums on both Chiplets and 3D IC. There is a lot of buzz on both topics.

And TSMC’s SoIC initiative provides the manufacturing infrastructure and technical support to achieve next-generation innovation. Indeed, all the elements needed for 3D chiplet-based design are taking shape. It has been said that the devil is in the details. And the details and technical challenges to be overcome as we move to a new chapter in semiconductors are daunting. Meaningful progress to reduce these challenges is quite important, and that progress was on full display at the Alchip presentation. Let’s examine how Alchip is paving the way to future 3D design innovation.

Alchip at TSMC OIP

Erez Shaizaf

The presenter from Alchip was Erez Shaizaf, Alchip’s Chief Technical Officer. Erez has been with Alchip for the past two years. He has a long career in semiconductors with companies such as Freescale, EZchip, Mellanox, and Xsight Labs. Erez discussed how Alchip, working with Synopsys and TSMC, has overcome several significant challenges for 3D IC design in the areas of electrical, power, thermal and mechanical design.

Erez described the kind of 3D architecture being addressed as one that contains top dies in advanced nodes (e.g., high-frequency CPU) and bottom dies in older nodes (e.g., memory subsystems). A coherent fabric connects the two layers with an Alchip Micro 3D liteIO PHY interface. Fine pitch hybrid bonding and fine pitch TSVs create high bandwidth interconnect and efficient power delivery between the top and bottom dies. The figure below illustrates this 3DIC folded CPU use case.

Erez also discussed several power delivery challenges, including:

  • Power Integrity Challenges
    • Static and dynamic IR drop
    • Power noise propagation from bottom to top die and vice versa
    • Different power domains among top and bottom dies and a shared ground plane
  • Power Grid Design
    • TSV distribution
    • B distribution
    • PDN design
  • Power Integrity Simulation and Signoff
    • Early analysis (prior to place & route)
    • Early simulation (after place & route)
    • Signoff

The paper also described a sophisticated TSV distribution strategy that uses non-uniform and location-dependent TSV arrays. Using this approach, TSV density is determined by local power density for bottom and top die shared and non-shared power delivery networks (PDNs).  Erez detailed the pros and cons of shared vs. non-shared PDNs. He explained that non-uniform TSV density schemes are friendly to automated place & route. The TSV patterns are compatible with Alchip’s multiple 3D-liteIO micro-PHY P&R and TSMC design rules.

Erez also talked about how to do early PDN analysis and the benefits that result. He also discussed how to achieve 3D data and clock design targets and details of an H-tree strategy for 3DIC clocking. 3DIC thermal characterization challenges and solutions were also presented, along with a set of verification strategies aimed at 3DIC design.

Abhijeet Chakraborty

Abhijeet Chakraborty, Vice President Engineering at Synopsys, followed Erez to the podium. Abhijeet has been with Synopsys more than 18 years. He described how the Synopsys 3DIC Compiler delivers a unified exploration-to-signoff platform. The benefits of this platform include:

  • Extending 2D fusion platform (Fusion Compiler) for 3D heterogenous integration (3DHI) and advanced packaging
  • Delivering a unified environment that supports 3D design exploration, planning, implementation and verification
  • Integrating the golden signoff solutions from Synopsys and Ansys for 3D STA, EM/IR, SI/PI/TI, EMAG
  • Providing full support for TSMC technologies including CoWoS, SOIC, and 3Dblox

Overall, Abhijeet explained that Synopsys and Alchip are collaborating on HPC/AI-optimized physical design for advanced nodes, IP and multi-die packaging. The graphic at the top of this post provides a high-level summary of how Synopsys and Alchip are enabling 3DIC design success.

The Implications of This Work

I had a chance to speak with Erez Shaizaf after the presentation. He gave me some perspective on the implications of the work presented. In a word, it’s transformative.

Erez explained that up to now, most multi-die designs consisted of active devices, like AI accelerators and some HBM memory stacks over passive devices, like caps and interconnect supplied by the interposer. The work presented at OIP opens the possibility for multiple active devices in the stack to come from different technology nodes. He predicted these new options will change the designer’s mindset and system design will take on new meaning.

He explained that the ability to integrate multiple active devices in a true 3D stack with multiple process nodes opens many new options for system architecture and integration. One benefit of this approach is partitioning a subsystem from one large die to multiple smaller dies. This delivers a yield and cost benefit. There are many more examples of how a more unconstrained 3D design flow can change the game.

He pointed out that the yield, thermal, mechanical and power delivery aspects of true multi-dimensional system design are substantial. The way design will be done will change as well. But the opportunities for true system innovation make it all worthwhile.

Erez concluded by saying that Alchip and Synopsys are breaking down the barriers to this new design paradigm. Along with TSMC, they are bringing new opportunities for innovation within reach, and that makes for an exciting future.

To Learn More

You can find out more about the TSMC Global OIP Ecosystem Forum here.  If you are considering the benefits of 3DIC design, you will want to learn more about how Alchip can help. You can access more information about Alchip here. Even better, you can reach out to the company to discuss your future design needs here. And that’s how Alchip is paving the way to future 3D design innovation.

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Handling Objections in UVM Code

Handling Objections in UVM Code
by Daniel Payne on 11-18-2024 at 10:00 am
Categories: EDA, Siemens EDA

expanded view min

You begin writing some UVM code and there are parts of the code that aren’t done yet, so you begin to use uvm_objection, guarding that code. Rich Edelman, a product engineer at Siemens doing verification debug and analysis, wrote a paper on this topic, which I just read. This blog covers the topic of objections and provides some different approaches.

UVM is founded on processes, and processes can be synchronized automatically or by design during phases. We typically raise an objection, then later on drop the objection during a phase.

Here’s a UVM example using a raised objection to make sure that simulation doesn’t exit until a drop exception happens.

The source code of has over 1,000 lines of code, so it’s recommended to use objections once in a test. Consider a UVM test with four sequences, using raise_objection and drop_objection.

Each of the four environments (e1 – e4) call raise_objection and drop_objection, which is not so efficient.

A simpler objection in UVM is the uvm_barrier.svh, at just 240 lines, but we can define our own barrier function with even fewer lines like this:

This barrier code uses a count to pass the barrier. When the count reaches 0 after a drop, it exits.

Another approach to synchronization is using names like start, middle, and end.

 

This wrapper creates the barrier class if needed, and uses three names: raise, drop, and get.

The next example shows a class and a module, where there are two class instances and three Verilog modules. Three phases are synchronized across the modules and class instances: start, middle, and end. The objects simulate in each phase for some time, then drop the objection. After all objects have dropped, processing continues.

Running this example shows that each object reports after “drop” has returned, then each object moves forward.

Both Class1 and Class2 are SystemVerilog class handles, while A, B, and C are the Verilog module instances. Each of the objects in each phase waits until the next barrier completes, which is our synchronization goal.

Below are visualizations: the “middle” phase and the workload for each object. Each phase—here the middle phase—displays each object: “class1,” “B,” “A,” “class2” and “C,” in order, along with the payload for each object.

This view shows many phase begins and ends, all synchronized.

The expanded view provides details of the objects and payloads in each phase.

Objections and phasing are linked together, so use objections with phasing while limiting their usage to be more efficient. One way to create phasing is through a barrier like uvm_barrier, or using the examples presented. You can solve synchronization with your own code. Adding too many raise_objection and drop_objection pairs in your code will only slow down simulation times.

Summary

Yes, continue to use uvm_objection in your UVM code, being careful to not slow down run times by calling it too often. Alternative approaches were shared in this blog that require less code, are more intuitive, and run quicker.

Read the complete 15 page paper online.

Related Blogs

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GaN HEMT modeling with ANN parameters targets extensibility

GaN HEMT modeling with ANN parameters targets extensibility
by Don Dingee on 11-18-2024 at 6:00 am
Categories: EDA, Keysight EDA

Modified ASM HEMT equivalent circuit for GaN HEMT modeling with ANN parameters

Designers choosing gallium nitride (GaN) transistors may face a surprising challenge when putting the devices in their context. While the Advanced SPICE Model for GaN HEMTs (ASM-HEMT) model captures many behaviors like thermal and trapping effects, it grapples with accuracy over a wide range of bias conditions. Foundries often define ASM-HEMT parameters from measurements at a specific bias point but don’t solve for different bias values. Keysight device modeling researchers are exploring an improved ASM-HEMT hybrid model, blending measurements with physics and using artificial neural network (ANN) techniques for improving wide-range S-parameter fit in minutes. We spoke with Rafael Perez Martinez, R&D Software Engineer in the R&D Device Modeling group at Keysight EDA, about this new approach to GaN HEMT modeling with ANN parameters.

A choice between lengthy measurements or less-than-accurate simulations

Perez Martinez began his exploration of GaN HEMT modeling at Stanford University, working on his PhD in the Wide-Bandgap Lab (WBGL). “I had an idea in 2022 looking at prior ASM-HEMT publications. It seemed like people weren’t reporting CV characteristics fitting, and they tended to fit the model at one drain voltage bias,” he says. “Measurements are tedious, and measurement-based models such as DynaFET require extensive DC and S-parameter data and large-signal non-linear vector network analyzer (NVNA) measurements that can take one to three months to set up and execute.” Physics-based theoretical models like ASM-HEMT can readily simulate and extend S-parameter predictions across frequency ranges but tend to inaccurately fit parameters at varying bias voltages.

Additionally, many university labs and start-ups don’t have budgets for an NVNA or similar instruments and accessories for GaN HEMT measurements. Perez Martinez parlayed his summer internships at Keysight into a WBGL proposal for grant funding for a Keysight PNA-X, which arrived at the lab in 2023. With coaching from Keysight teams, Perez Martinez dove in, taking PNA-X readings on a 150nm gate length GaN-on-SiC HEMT and capturing its non-linear characteristics. Plugging the measured parameters as-is into a standard ASM-HEMT model highlighted the disparity between the two approaches. The S-parameter fitting performs poorly with VD=5 to 25 V, VG=-3 to -1V, and f = 250MHz to 50GHz (measurements in red, simulations in blue).

Moving to hybrid GaN HEMT modeling with ANN parameters

This persistent mismatch between measurements and simulation gave Perez Martinez the idea of developing a hybrid model example, combining the baseline of a measurement-based model with the extensibility and speed of physics-based modeling. “I had GaN HEMT measurements at 10 GHz with second and third harmonics,” he says. “But starting the hybrid model was difficult initially because you need to know the device model, go through the Verilog code, know what to change – and you can’t just add things randomly. There has to be some physical aspect of any change that makes sense.”

With measurements in the 10 GHz region where the model should be most accurate, Perez Martinez moved into Keysight IC-CAP for modeling with its ANN Modeling Toolkit. “Integrating a neural network into the Verilog model is quite trivial using the ANN toolkit,” continues Perez Martinez. “Looking at some earlier small-signal models, I noticed the ASM-HEMT model was missing something around gate-drain resistance, so that’s where I started, working carefully not to fix one problem and break something else.” A few cycles of replacing parameters with ANN variables and using the IC-CAP optimizer added two resistances and three capacitances to the ASM-HEMT equivalent circuit (inside the dotted pink outlines).

Generalizing results from ANN parameter fitting

A Keysight ADS simulation with hybrid ANN parameters from IC-CAP aligns very closely with measurements, as indicated by the near-perfect overlap between the red lines and the dotted pink lines in this comparison of power-added efficiency, gain versus Pout, and dynamic load lines. In this case, the model modification solves the problem of simulating wide-range bias.

The logical follow-up to this result: are these results device-specific, or will the methodology scale to smaller geometries and higher frequencies? “The first challenge is getting measurements at higher frequencies, which takes access to instrumentation, plus time and care,” observes Perez Martinez. “The next challenge is not every GaN HEMT has the same physical device structure, and people tend to play tricks – maybe the distance between the drain and gate varies, maybe there’s a different field plate, or maybe the gate structure has a different shape.” The implication is that one model may not fit all devices. However, the ANN approach in IC-CAP works with any device model and helps narrow down where modifications can improve and speed up S-parameter fitting – in a matter of hours versus months of measurements.

That’s an important observation since Perez Martinez is not necessarily looking for a formal ASM-HEMT model update. He’s presenting his paper at the IEEE BiCMOS and Compound Semiconductor Integrated Circuits and Technology Symposium (BCICTS) to raise awareness and generate discussion around the approach. “People always talk about positive results in papers, but rarely do they talk about the failures it took to get there,” says Perez Martinez. “This is really a look at some GaN HEMT model shortcomings we’ve seen, and a hybrid model example in IC-CAP with ANN that we’d like people to look at that might fit their needs.”

To see more details about the methodology for GaN HEMT modeling with ANN parameters and the results, see the BCICTS 2024 paper in the  BCICTS proceedings archive:

A Hybrid Physical ASM-HEMT Model Using a Neural Network-Based Methodology

Also, see more information on the latest in GaN device modeling from Keysight experts:

Electronic Design webinar:   Mastering GaN Device Modeling

Keysight:   Device Modeling IC-CAP   |   W7009E PathWave IC-CAP ANN Modeling Toolkit

Also Read:

Keysight EDA 2025 launches AI-enhanced design workflows

Webinar: When Failure in Silicon Is Not an Option

Keysight EDA and Engineering Lifecycle Management at #61DAC

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AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 – China & Delays & CHIPS Act?

AMAT has OK Qtr but Mixed Outlook Means Weaker 2025 – China & Delays & CHIPS Act?
by Robert Maire on 11-17-2024 at 8:00 am
Categories: Semiconductor Advisors, Semiconductor Services

Applied Materials

– AMAT has OK QTR but outlook below expectations as 2025 weakens
– Strength in AI cannot offset weakness in the rest of the market
– Increasing headwinds going into 2025 dampen overall outlook
– Weakness combined with regulatory uncertainty reduce valuations

Quarter and year are just OK but outlook is weak/mixed

Applied Materials reported revenues of $7.05B and non GAAP EPS of $2.32 modestly better than expectations of $6.97B and $2.19.

Guidance is for revenues of $7.15B +-$400M and $2.29+-$0.18 versus street of $7.25B and $2.27.

Body language and discussion on the call was not very assured nor certain about 2025. Actual system sales were not that great but service revenues helped offset systems weakness.

Year over year growth was minimal at 2%.

Hard for AI to drag an overall weakening semiconductor industry along

While we hear a lot of talk about AI, we keep repeating that its less than 10% of memory and only the very bleeding edge of a single foundry , TSMC. The vast majority of memory, two of the 3 big players (Samsung & Intel), trailing edge nodes are all weak with negative momentum.

As we pointed out in our note this past Monday there has been near term additional negative news of Micron’s delay and other order delays.

CHIPS Act risk & China risk add to uncertainty

When asked about the new incoming administration, management demurred rather than reacting positively as prior comments on the CHIPS Act create open questions.

China is down to about 30% but 30% is still the largest slug of Applied business so losing China would be a horrible hit.

Tariffs and other draconian regulatory issues add to potential China risk in addition already declining demand.

Results and outlook supports our ongoing concerns

In our note this past Monday we said “News flow for semi equipment all bad in front of AMAT”.

Link to our recent note

Applied’s report and outlook only support our ongoing concern/predictions about a weaker 2025 and worsening near term data points.

We would reiterate that this in no way implies that AI is weak or has any fundamental issues….quite the contrary, we think AI remains super strong and is tremendously positive for semiconductor equipment. Without AI, semiconductor equipment would be in a freefall right now.

The simple fact is that 10% or less of the chip industry that is on fire , can’t hope to make up for the other 90% that is weak or muddling along at best….

The Stocks

We had warned investors to “lighten up” in front of Applied’s earnings as we saw much more downside beta than potential upside beta.

Applieds stock was off over 5% in after market trading as investors were clearly unhappy with the poor outlook

There will obviously be collateral damage to the semi equipment group as 2025 concerns are not contained to just AMAT.

ASML stock recently saw a nice pop as it reaffirmed its long term revenue and financial model over the next few years (which we heartily agree with). The question is clearly about 2025….is it up, down or sideways….longer term, for semiconductors and semiconductor equipment, is always up and to the right …

There had been an initial, more positive view by many analysts which now appear too optimistic and will have to be trimmed to be more conservative, to the view we have long held, of a slower recovery with more lumps and bumps along the way

We hope you still have your seat belts on as the near term turbulence will continue!

About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash

LRCX- Coulda been worse but wasn’t so relief rally- Flattish is better than down

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake

Podcast EP261: An Overview of the Upcoming 70th IEDM with Dr. Gaudenzio Meneghesso

Podcast EP261: An Overview of the Upcoming 70th IEDM with Dr. Gaudenzio Meneghesso
by Daniel Nenni on 11-15-2024 at 9:00 am

Dan is joined by Dr. Gaudenzio Meneghesso, IEDM 2024 Publicity Co-Chair, and Head of the Department of Information Engineering at the University of Padua in Italy.

Dan explores the program for the upcoming IEDM event with Gaudenzio. This conference covers a wide range of innovations that have significant impact on the semiconductor industry.

Gaudenzio discusses four “grand challenges” that will be explored at IEDM: Device scaling,memory architectures and in-memory compute, chip packaging and power efficiency. In the area of power efficiency, the impact of new devices based on compound semiconductor technology will be explored.

The demands of AI performance and the associated impact on semiconductors will also be presented. Other high-profile topics include nano-sheet transistors and high-density aligned carbon nanotubes, among others.

The 70th IEDM will be held December 7-11, 2024 in San Francisco. You can learn more about this important conference and register to attend here.

The views, thoughts, and opinions expressed in these podcasts belong solely to the speaker, and not to the speaker’s employer, organization, committee or any other group or individual.

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More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay

More Headwinds – CHIPS Act Chop? – Chip Equip Re-Shore? Orders Canceled & Fab Delay
by Robert Maire on 11-15-2024 at 8:00 am
Categories: Semiconductor Advisors, Semiconductor Services
4 Comments

CHIPS Act Semiconductor USA

– CHIPS Act more likely to be maimed & cut than outright killed
– Will Legislators reverse flow of equipment to Reshore from Offshore?
– Recent order cuts, Fab Delay & SMIC comments are all negative
– News flow for semi equipment all bad in front of AMAT

CHIPS Act Chops likely to occur under new administration

In the days leading up to the election, Trump made it crystal clear he thought the CHIPS Act was a “bad deal”. Then Mike Johnson, following his lead said he would probably want to repeal the CHIPS Act.

Even though some analysts and investors will say the incoming administration can’t do anything because deals are signed, there is certainly plenty that can be done to delay, prevent, modify, question and generally screw with even a done deal….especially if you are the new administrator, who writes the checks, of said deal.

We don’t think that the deal with Intel will get torpedoed but the TSMC deal has some risk. Samsung Texas will likely get done. Micron in Idaho is probably safe but the Micron Clay, New York fab is likely toast.

We think the administration will also look to undo the chip design center in California just to spite a Blue state and Newsome. Likewise Clay New York was Schumer’s baby in an also very blue New York state.

No matter what, its going to be different than anticipated as the incoming administration will influence it much as the outgoing administration influenced it.

Take a look at the electoral map then look at the CHIPS Act map if you want an idea:

At the end of the day, reduced CHIPS Act spend is most directly less spend on semiconductor equipment as 90% of the cost of a new fab is in the equipment…

Cancellations & delays last week

We heard of some large cancellations coming out of a large US chip maker last week. Although likely anticipated its always a negative when it actually happens.

We also heard that Micron’s new Idaho Fab has been delayed. While this is not a near term issue it adds to the increasing headwinds. It also increases the chances of Micron’s Clay NY fab to be further delayed if not outright canned.

SMIC comments on China semi equipment indigestion

Adding to the cancelation/delay headwinds we heard from SMIC, China’s largest fab that orders for equipment coming out of China will be down as trailing edge capacity is over supplied.

Although this is something we already know and already heard about slowing China orders it is just confirmation that China is up to their eyeballs in equipment and already has way to much.

Over supply situations like this can take years to fix as not only is there too much current trailing edge supply but we also have a pipeline of equipment that hasn’t even been turned on yet.

The “Captain Obvious” award of the week goes to US legislators that finally figured out chip equipment is still be offshored, while trying to reshore chips.

US legislators sent letters to AMAT, LRCX, KLAC, Tokyo Electron & ASML asking what was up with their sales of chip equipment to China. But perhaps more importantly the letter asked about where the equipment is being made and the supply chain of that equipment.

Select committee on CCP Chips

SCMP article

NY Times article

This topic is something we have been talking about longer and more vocally than anyone else.

It seems insanely stupid and short sighted to “re-shore” semiconductors while you continue to “off-shore” the equipment made to produce them.

Wouldn’t it be just plain dumb to move chip manufacturing back to the US only to have equipment made by US companies in Asia imported back into the US where all the equipment used to be made?

Applied Materials has been the leader in moving production out of Texas to Singapore. Lam is not far behind in moving all its California and Oregon based manufacturing to Malaysia. Lam recently crowed about shipping its 5,000th chamber out of Malaysia.

Could the US finally get its act together and force chip equipment makers to reshore that which they have off shored so quickly just over the past few years? Its not like Taiwan or China stole the US equipment industry. The industry has been moving to Asia as fast as humanly possible for primarily financial reasons.

It would be yet another problem/headwind for equipment makers. The huge cost of moving only to have a large cost to move back. Lower margins and higher costs due to increased costs in the US that led them to leave in the first place.

The incoming administration could even put a tariff on imported chip equipment much as they will likely put a tariff on imported chips to force manufacturers to move back to the US as this is a core of the platform Trump was running on.

It could get ugly.
The Stocks

The recent election results raised all the boats in the stock market to new highs.

We would point out that the actual impact on the semiconductor and especially the semiconductor equipment stocks are not quite so positive especially over the longer run given both recent and future headwinds.

The CHIPS act will be likely negatively impacted, its only a question of how much. China and Tariffs will only get worse and likely impact chip production and equipment.

Near term headwinds continue to slow the overall market and most recent news is certainly negative.

It may not be a bad time to think about reducing exposure to some of the more impacted names in the space before everyone figures out the potential negative impacts.

Buckle up, things will change, a lot.
About Semiconductor Advisors LLC

Semiconductor Advisors is an RIA (a Registered Investment Advisor),
specializing in technology companies with particular emphasis on semiconductor and semiconductor equipment companies. We have been covering the space longer and been involved with more transactions than any other financial professional in the space. We provide research, consulting and advisory services on strategic and financial matters to both industry participants as well as investors. We offer expert, intelligent, balanced research and advice. Our opinions are very direct and honest and offer an unbiased view as compared to other sources.

Also Read:

KLAC – OK Qtr/Guide – Slow Growth – 2025 Leading Edge Offset by China – Mask Mash

LRCX- Coulda been worse but wasn’t so relief rally- Flattish is better than down

ASML surprise not a surprise (to us)- Bifurcation- Stocks reset- China headfake

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CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix

CEO Interview: Dr. Sakyasingha Dasgupta of EdgeCortix
by Daniel Nenni on 11-15-2024 at 6:00 am
Categories: CEO Interviews

Sakya Dasgupta 2024

Sakya is the founder and Chief Executive officer of EdgeCortix. He is an artificial intelligence (AI) and machine learning technologist, entrepreneur, and engineer with over a decade of experience in taking cutting edge AI research from ideation stage to scalable products, across different industry verticals.  He has lead teams at global companies like Microsoft and IBM Research / IBM Japan, along with national research labs like RIKEN Japan and the Max Planck Institute Germany. Previously, he helped establish and lead the technology division at lean startups in Japan and Singapore, in semiconductor technology, robotics and Fintech sectors. Sakya is the inventor of over 20 patents and has published widely on machine learning and AI with over 1,000 citations.

Tell us about your company?
We are a fabless semiconductor company focused on enabling energy-efficient and sustainable artificial intelligence processing that will scale from edge computing to servers. I founded the company in 2019 with our development headquarters in Tokyo, Japan and we have now expanded our operations into both the United States and India. We deliver a software-first approach to AI focused processors, with our patented “hardware and software co-exploration” system to bring to market a unified edge AI acceleration platform. This platform provides an end-to-end solution for our customers with our MERA software and latest SAKURA low-power AI inference accelerators.

Our customers span a wide array of industries, including smart cities, robotics, manufacturing, aviation, aerospace, security, and telecommunications. While these industries are distinct and serve unique purposes, they all share a common goal of deploying extremely low power, high performance AI solutions at the edge. The edge is where the vast majority of data is now being created and collected, and because critical business decisions are being made there continuously, these decisions must be made accurately and securely. The other commonality between these industries is that they demand a combination of real-time processing, tight power restrictions and low-latency. This is where EdgeCortix’s solutions lives and excels, offering specialized hardware and software solutions to meet these demanding criteria.

What problems are you solving?
EdgeCortix was founded with the principal goal to solve the AI performance and power inefficiency challenges ‘at the edge’.  Our core mission is to democratize access to all types of AI solutions by solving the fundamental mission of enabling near cloud-level AI performance at the edge, with better energy efficiency and speed, drastically reducing customer operating costs. Today, it is truly incredible to see how the latest generative AI and multi-modal AI applications are expanding so rapidly in the marketplace. These AI applications however, typically require massive computational and electrical power, which is tough at the edge where being performant, while maintaining energy-efficiency is critical. EdgeCortix has developed an industry leading, energy-efficient, ultra-low latency software and hardware acceleration platform, powered by our latest SAKURA-II devices that accelerates these multi-modal generative AI workloads, and empowers its customers to solve their edge-based challenges.

What application areas are your strongest?
Four industries where we have been seeing the most prominent demand, includes smart cities, industrial applications, aerospace and security. As municipalities implement more Smart City functionality, they face a variety of challenges in adding AI capabilities to analyze issues such as traffic congestion and security. Ultimately, smart surveillance can apply to any gathering place in a city with networks of cameras providing high-resolution video from many angles and collecting volumes of data. Using AI inference to accurately recognize people and items has the potential to keep citizens safe in crowded spaces in case of an emergency. From an industrial perspective we find the most traction in smart manufacturing – an area right now with so much potential for improvement in both production, cost savings and safety. In factories, edge AI solutions can enable optimization of production lines, predict equipment failures, and enhance quality control.

Real-time analysis of sensor data helps improve efficiency and reduce downtime. In the aerospace industry, our SAKURA-II solutions can assist in aircraft maintenance, provide quality assurance in manufacturing, and most importantly is a critical enabler for adding AI capabilities. It can ensure safety and reliability, all while minimizing maintenance costs. Last but not the least, we are very excited about the prospects of our AI processors being applied in the space industry from low-earth orbit to outer space environments. In this regard, the proven ability of our SAKURA devices to survive outer space radiation impact significantly better compared to comparable commercially off-the-shelf processors, as recently tested by NASA, opens up a variety of applications.

What keeps your customers up at night?
What keeps our customers up at night fuels our relentless focus during the day. We must solve for the edge AI performance and power inefficiency challenges. Our customers, no matter what industry they serve, are trying to do more with less. Less space, less cost, less power and less heat are all critical considerations, and our ability to deliver high performance and high efficiency while meeting these constraints is highly valued by our customers. In addition to these factors, a critical consideration point for all our customers has been software robustness. Every day we are considering how we can augment our software and solutions to help drive improved performance based on our customers’ unique needs. EdgeCortix operates on a global scale with teams spanning from Asia to North America. We are dedicated to fulfilling our customers’ needs around the clock.

What does the competitive landscape look like and how do you differentiate?
Our goal is to meet our customers where they are in their technology stack and to help to future-proof their operations. I believe that we are in a truly unique market position. Many companies focus on either the hardware or the software, but the way in which we’ve developed our platform is unique. We apply equal importance to software development and chip design, and we started with software-first, and then enabling a robust hardware ecosystem. In addition to our patented run-time reconfigurable processor, the flexibility of our software and our ability to easily integrate within existing heterogeneous hardware platforms is not something we’re seeing made available from the rest of the industry today.

What new features/technology are you working on?
The SAKURA-II Edge AI platform is a complete AI solution comprised of three elements, the SAKURA-II silicon device, the Dynamic Neural Accelerator® (DNA) runtime reconfigurable (IP) neural processing architecture, and our MERA heterogeneous compiler software platform. We implement these technologies on a selection of hardware from M.2 modules, PCIe cards and compute boxes for immediate AI system deployment by our customers.

SAKURA-II is optimized for applications requiring fast, real-time (Batch=1) AI inferencing with excellent performance in a small footprint and low power silicon device. SAKURA-II is designed to handle the most challenging multi-modal AI applications at the edge, enabling designers to create new content based on disparate inputs like images, text, and sounds, and supports multi-billion parameter models like Llama 3, Stable Diffusion, DETR, Mistral, and ViT within few Watts of power.

Our Dynamic Neural Accelerator (DNA) is a flexible, modular dataflow architecture with our proprietary run-time reconfigurable data path connecting all major compute engines on chip, achieving exceptional parallelism and efficiency through dynamic grouping. Using a patented approach that combines sparsity handling, power management techniques, mixed precision support, vector and tensor processing, DNA achieves outstanding parallelism while reducing on-chip memory bandwidth, allowing faster, more efficient hardware execution.

MERA is a compiler and software framework providing a robust platform for deploying the latest neural network models in a machine learning framework agnostic manner. MERA enables optimized deep neural network graph compilation and inference, while providing the necessary tools, APIs, code-generator, and runtime libraries needed to deploy any pre-trained deep neural network from convolutions to the latest transformer models. MERA is designed to handle the most challenging AI applications at the edge with interfaces to open-source platforms like Hugging-Face as well as a rapidly growing EdgeCortix Model Library, enabling designers to create new content or deploy from a wide variety of existing models. MERA’s built-in heterogeneous support for other leading general-purpose processors, including AMD, Intel, Arm, and RISC-V, allows quick integration into existing systems.

How do customers normally engage with your company?
Our customers typically engage with us in the following three ways:

  • Software: Customers who purchase a SAKURA solution will automatically access the EdgeCortix MERA Compiler software framework to deploy AI acceleration within their existing environments. In select cases we have also licensed our software to enable integration with other third-party Arm and X86 based hardware platforms, enhancing the overall ecosystem support.
  • AI Accelerator Devices: EdgeCortix offers the latest SAKURA-II devices for purchase, a 60 TOPS (INT8) / 30 TFLOPS, yet small, low-power, mass produced product suitable for edge computing.
  • AI Accelerator Cards & Modules: Customers can use our AI Accelerator hardware to directly integrate into their systems or solutions (orders available now). EdgeCortix currently offers SAKURA-II hardware in single and multi-chip low-profile PCIe Card and M.2 Module form factors.

We can be reached via the following:
Our contact page: https://www.edgecortix.com/en/contact
Our website: https://www.edgecortix.com/en/
Our LinkedIn: https://www.linkedin.com/company/edgecortix/

Also Read:

CEO Interview: Bijan Kiani of Mach42

CEO Interview: Dr. Adam Carter of OpenLight

CEO Interview: Sean Park of Point2 Technology

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Analog IC Migration using AI

Analog IC Migration using AI
by Daniel Payne on 11-14-2024 at 10:00 am
Categories: Cadence, EDA
2 Comments

Analog Migration with virtuoso studio

My first job out of college was migrating a DRAM chip from one process node to a newer node, and it was a 100% manual process that required many months of effort. That need to migrate semiconductor IP to newer nodes is still with us today, and much automation has been applied to digital circuits, however migrating analog IP has proven to be much more challenging to automate. I spoke with Girish Vaidyanathan, Product Management Director at Cadence to learn how their Virtuoso Studio tools were enabling AI-driven, custom design migration.

IC design companies want higher productivity, and faster turnaround time to enable the promises of IP design reuse as they move from one node to a newer node, staying within the foundry partner ecosystem or even moving to another foundry. Ideally, during an IP migration the design intentions should remain the same, for example, matching and shielding requirements. Any automation for migration needs to understand the design intents, while at the same time conforming to the new PDK being targeted.

Early migration approaches with older nodes used more of a Lambda scaling when process nodes were at 180nm or larger dimensions, but today each new process generation doesn’t scale with Lambda, so the non-uniform scaling of transistors, interconnects, contacts and vias requires a much smarter approach to migration. The IC layout approaches dramatically change when migrating from planar to FinFET, and FinFET to GAA.

What Cadence has put together in Virtuoso Studio is an AI-powered flow that accepts schematic and layout as inputs, infer the design intentions, apply mapping from the foundry source to target, transform the source schematic to a target schematic, optimize the parameters of the devices to make the circuit meet the target specifications, and automates the layout migration process.

The schematic migration flow is shown in more detail in the customer presentation at Cadence Live:

Schematic Migration

A testbench from the Virtuoso ADE Suite is rerun to see if the specifications are met, and optimizations are run after updating parameters to meet the new specifications. The optimization helps meet the specifications across all PVT corners. ML techniques are used to infer optimizations. The design space is too large for analog designs, so non-gradient based techniques are used for optimizations. ML techniques are also applied during the creation of the new layout.

I learned that during circuit simulation in this optimization flow you can use Cadence or other SPICE circuit simulators. Your CAD team can even use a custom optimizer in the flow by coding in C++ or Python. There’s the Virtuoso ADE framework to manage circuit simulations, so you can use the Cadence optimizer or your own. Cadence developers have spent the last three years on this automated migration flow. You can even have Cadence do an IC migration for your project, as a service option.

The layout migration flow is shown below and has several steps where you guide the tool to get the best results that meet specifications:

Layout Migration

Girish showed me a sample analog layout that was migrated using Virtuoso Studio where automated place and route demonstrated a 2X productivity gain over manual methods:

Source and target layouts

For Cadence customers there are four interesting videos from CadenceLIVE events that highlight several use cases for analog IC migration:

  • Samsung – schematic migration
  • Global Foundries – schematic migration, AI/ML-driven optimization, layout migration
  • TSMC – RF migration
  • Intel – layout migration

Summary

Migrating custom and analog IP is a challenging engineering task that can be done either manually or with the help of automation. Cadence has created an automated migration flow that is producing some impressive results in saving time and reducing engineering effort by using ML-based optimization in the flow. Major customers have already been using the flow, so it’s safe to give it a look for your own migration projects

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Next Generation of Systems Design at Siemens

Next Generation of Systems Design at Siemens
by Daniel Payne on 11-14-2024 at 8:00 am
Categories: EDA, Siemens EDA
1 Comment

New, Unified GUI

Electronic systems design is filled with a wide range of tools used across IC packaging design, multi-board systems, design creation, physical implementation, electro-mechanical co-design, simulation & analysis, and new product introduction. Siemens has been offering tools in this flow for many years now, so I was able to meet by video with David Wiens, Product Marketing Manager to get briefed on their next generation release. The following three EDA tools have a new, unified GUI, along with cloud connectivity and AI smarts:

  • Xpedition – electronics system design for enterprise use
  • HyperLynx – high-speed system analysis and verification
  • PADS Professional – low-cost, integrated PCB design

The vision at Siemens is to enable integrated, model-based system engineering, so that teams of engineers working across the multiple domains of software, electrical, electronics and mechanical can collaborate throughout the design process. Industry trends reveal a workforce in transition, with a general shortage of engineers, mass electrification of industrial products, and volatility in the supply chain across the globe. We are now in a new era where AI techniques are being applied to the electronic design process, the cloud is used to connect the work of teams, and using EDA tools through intuitive GUIs improves productivity.

Next Generation

Across the new release of Xpedition, HyperLynx and PADS Professional tools you quickly notice the consistent GUI, which has a modern look using more icons, arranged in groups based on function. Engineers will experience a short learning curve, making them more productive across the flow of these tools. Users can personalize how their icons are arranged, or even opt to go back to the classic look.

New, Unified GUI

As an engineer is using these tools there are AI-infused, predictive commands appearing in the menu, based on the patterns. Each customer will see their own predictive commands, based on their tool usage, and they can have an expert train their own model and share that within an organization. Engineers can also use natural language to find new components for their system design. Simulations are optimized to use predictive selection, so a design can be optimized without resorting to brute-force simulations across a large number of permutations, allowing you to explore the design space in a reasonable amount of time. Doing SI/PI analysis on a large system can now be run overnight, instead of waiting hundreds of days.

Predictive Commands

These next generation of tools are also integrated with other Siemens products, like: Teamcenter, NX and Simcenter, to support multi-domain design. There is partner PLM integration too, with Dassault and PTC. Model-based engineering happens through requirements decomposition and verification management in Xpedition.

Teams of engineers collaborate in real-time using a cloud-connected environment, enabling easier design reviews, getting insight to supply chain availability, performing component research and sourcing, and even ensure manufacturability through DFM profile management. RoHS compliance can be met using supply chain insights from Supplyframe. Assuring IP integrity, accuracy and reliability is security through managed access control based on each user’s role, permission and geography.

Summary

Siemens has released a new version for Xpedition, HyperLynx and PADS Professional that sports a new, unified, modern GUI, making life more productive for PCB designers. AI features also benefit users, through anticipating their next menu item and optimizing the number of simulations required. Collaboration is improved through cloud connectivity, making communication between team members faster. The PCB tools integrate throughout the systems design flow with both Teamcenter and NX software, enabling multi-domain design and analysis.

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Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit
by Mike Gianfagna on 11-14-2024 at 6:00 am
Categories: AI, Events, Samtec, Semiconductor Services

Samtec Paves the Way to Scalable Architectures at the AI Hardware & Edge AI Summit

AI is exploding everywhere. We’ve all seen the evidence. The same thing is happening with AI conferences. The conference I will discuss here began in 2018 as the AI Hardware Summit. The initial venue was the Computer History Museum in Mountain View, CA. Like most things AI, this conference has grown substantially in a relatively short period of time.  As you will notice, its name has grown, too to encompass a larger mission. At the recent event, there was significant focus on scalability in the deployment of AI systems. Samtec was there to address this challenge head-on. I’ll provide a summary here of the company’s presence at the show and how Samtec paves the way to scalable architectures at the AI Hardware & Edge AI Summit.

Samtec’s Presentation

At the show, Matt Burns, global director of technical marketing at Samtec presented Optimizing Data Routing in Copper & Optical Interconnects in Scalable AI Hardware Architectures. A rather long title, but there is a lot to address here.

Let’s take a look at the some of the topics Matt covered.

AI Agents

Over the past few years, Gen AI has been a driver in the adoption of AI agents. ChatGPT was just a pivot point. Applications such as text-to-chat/audio/image/video are redefining the customer experience in many industries. The next revolution in AI capabilities will be using AI agents to supplement the user’s experience.  The new “co-pilots” we are seeing from companies like Microsoft are good examples of this.  Other examples are actually improving code generation for simplicity and efficiency in real-time for developers.

Enterprise AI

Similarly, Gen AI has been the driving force behind enterprise AI adoption. However, only a fraction of the Fortune 1,000 has really started implementing AI to improve processes internally.  As enterprises discover how to use AI foundation models or application-specific models with their own internal data, AI will then begin to impact the bottom line for innovative companies.  The hyperscalers are leading the charge, but other companies will eventually follow.

Increasing model sizes requires more compute, but . . .

AI models are growing in size and scale. ChatGPT uses GPT-3.5 which has 175 billion parameters. GPT4 is rumored to approach 1 trillion parameters. Other models will soon approach 2 trillion parameters.  Model sizes are growing exponentially annually.  One GPU can’t handle all this.

Literally, hundreds if not thousands of GPUs need to be linked to parallel process the models. So, what’s the problem? AI compute performance is growing ~4.6x per year, but memory bus speeds are growing only ~1.3x per year and interconnect/fabric bus speeds growing only ~1.2x per year.  Those are the bottle necks.  Routing high-speed protocols like HBMx, CXL, PCIe and others over optics is becoming the trend.  Samtec demonstrated its CXL over optics solution at the show. The focus here is to position Samtec FireFly and Halo for some niche AI hardware applications.

Insatiable data center demand, but how are we going to power them?

More GPUs means more power. GPUs and other AI compute engines are approaching 2kW PER CHIP. That’s a lot of power.  System architects need to figure out how to get massive power into a rack and chassis efficiently and in small form factors at scale.

With these challenges as a backdrop, Matt presented the broad class of solutions for both copper and optical interconnect that Samtec offers. What is interesting about this show is that there are exhibits, but the footprint has always been limited to a table-top style of display. This keeps the focus on technology as opposed to fancy booth construction.

Samtec was at the show again this year, demonstrating its wide range of products for AI enablement.

Samtec booth at the show

To Learn More

If AI system scalability keeps you awake at night, Samtec can help. You can learn more about this unique company on SemiWiki here. And you can get an overview of Samtec’s AI capabilities here. You can even download a complete Artificial Intelligence/Machine Learning Solutions Guide here. As an aside, the conference is changing its name again. Next year’s event will be called AI Infra Summit. You can learn more about this change here.

And that’s how Samtec paves the way to scalable architectures at the AI Hardware & Edge AI Summit.