A SoC Design Flow With IP-XACT

A SoC Design Flow With IP-XACT
by Ranjit Adhikary on 07-27-2020 at 10:00 am

soc flow with ipxact

Taping out a SoC is never easy. The physical dimensions of the chip often belie the work which has been done to get to the tapeout stage. And it is still not a done deal as the hardware and software development teams await the arrival of the test chip from the foundry to complete the post silicon bring-up and validation. The pressure on… Read More


Webinar: Hassle-Free Bluetooth 5 SoC Design

Webinar: Hassle-Free Bluetooth 5 SoC Design
by Bernard Murphy on 01-05-2017 at 7:00 am


Bluetooth has always been a popular communication protocol for short-range applications, but now anticipating BT5 it’s really moving into the big leagues as a significant option for IoT applications. The new standard combines ultra-low power with significantly higher range and higher performance. Ultra-low power is always… Read More


5 ways FPGA-based prototyping shrinks design time

5 ways FPGA-based prototyping shrinks design time
by Don Dingee on 12-01-2015 at 7:00 am

Engineers are trained to think linearly, along the lines of we started here, then we did this, and that, and this other stuff, and here is where we ended up. If you’ve ever presented in an internal review meeting, sales conference, or a TED-like event, you know that is a dangerous strategy in winning friends and influencing people.… Read More


Making IP Reuse and SoC Integration Easier

Making IP Reuse and SoC Integration Easier
by Daniel Payne on 07-31-2014 at 2:00 pm

The last graphics chip that I worked on at Intel was functionally simulated with only a tiny display size of 16×16 pixels, because that size allowed a complete regression test to be simulated overnight. Our team designed three major IP blocks: Display Processor, Graphics Processor and Bus Interface Unit. We wanted to also… Read More