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5 ways FPGA-based prototyping shrinks design time

5 ways FPGA-based prototyping shrinks design time
by Don Dingee on 12-01-2015 at 7:00 am

Engineers are trained to think linearly, along the lines of we started here, then we did this, and that, and this other stuff, and here is where we ended up. If you’ve ever presented in an internal review meeting, sales conference, or a TED-like event, you know that is a dangerous strategy in winning friends and influencing people.

Boring CXOs, VPs, salespeople, and other mostly short-attention-span types to death usually results in being booed off stage before you get to show your key message. By showing people a summarized punchline right up front, they tend to engage and pay attention.

With that in mind, I’ll show you the last slide of a Synopsys presentation at ARM TechCon that probably should have been the first one:

The temptation is still to sell the concept of FPGA-based prototyping, but Neil Songcuan of Synopsys tossed out an interesting factoid: 75% of projects Synopsys is involved in are using some form of it, and that diagram is the reason.

Usage might be somewhat higher than an industry-wide design start figure because Synopsys is in the IP business and uses their own tools, creating artifacts that SoC designers who choose their IP can borrow to move into integration more quickly. More likely, it is because other Synopsys tools integrate with the HAPS family, shortening the time to perform tasks and reducing the overall development cycle (a message their sales team has probably embraced strongly).

Now we can back the camera up and look at the details. Neil cites 5 areas where the integrated Synopsys approach takes time out of the design cycle.

That first one, shortening the time to first prototype, is huge. I was speaking with other folks at ARM TechCon on that exact topic. If you are lucky enough to set up a prototype and it works the first time, fantastic, the extra time and effort plowed into first-time setup of FPGA-based prototype might seem long. In reality, few designs “work” the first time, and subsequent runs are almost certain.

The 1000 signals debug capability is from the new HAPS-80 with the Xilinx UltraScale inside, augmented with an onboard DIMM for deep trace capability. Complex protocols are tough to debug, and a long sequence must be observed to find issues. ProtoCompiler automates test point insertion and integrates with Verdi for improved GUI debug.

HAPS-80 is also offering performance in the vicinity of 10 MHz, enabling bigger swathes of production code and more scenarios to be executed in less time. Synopsys accomplishes this with hardware-aware guided partitioning that takes away much of the guesswork.

One of the big advantages of the Synopsys approach is exploration on IP blocks is done on more cost-effective HAPS platforms. The new and improved block is then rolled up incrementally into the integrated design on a larger HAPS system. Time advantage gained in subsequent runs after first setup can add up quickly, and after some number of runs depending on design size and complexity, the FPGA-based prototyping solution begins to pull away from alternatives in reduced cycle time.

Synopsys teams have been working hard to get the re-spin time down to overnight, so that productive work can resume right when teams arrive back from daily time with families. That <8 hour figure, even for very large designs, is impressive, allowing more iterations per day.

Bottom line: Synopsys is making strides in the overall user experience for FPGA-based prototyping systems, not just increasing capacity. Their end-to-end approach is looking at each possible step in development, gained from experience with both external and internal customers. For more on the HAPS-80 introduction, here is Paul McLellan’s post from a couple months ago.

FPGA Prototyping: From Homebrew to Integrated Solutions

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