This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.… Read More
One thing I do as an internationally recognized semiconductor blogger is listen to the quarterly conference calls of companies that drive our industry. TSMC is always interesting, I really like the honesty and vision of Dr. Morris Chang. Cadence is good, I always want to hear what Lip-Bu Tan has to say. Oracle and Larry Ellison, … Read More
At DesignCon this week there was a panel on 3D standards organized by Si2. I also talked to Aveek Sarkar of Apache (a subsidiary of Ansys) who is one of the founding member companies of the Si2 Open3D Technical Advisory Board (TAB), along with Atrenta, Cadence, Fraunhofer Institute, Global Foundries, Intel, Invarian, Mentor, Qualcomm,… Read More
The ASIC business is getting more and more complicated. The ability to produce innovative die at a competitive price to solve increasingly complex problems just isn’t enough. The technology required to package that die is now front and center.
Here, at the junction of advanced design, process technology and state-of-the art … Read More
Looking at the huge gap between the revenue of semiconductor design and manufacturing (~$300B) and that of EDA tools, services and silicon IP combined (~6B) inspired me to look more deeply into the overall arena of semiconductors in today’s context and possibly decipher some trends which should emerge in near future. Although… Read More
Advanced process technologies for manufacturing computer chips enable more functionality, higher performance, and low power through smaller sizes. Memory bits on a chip are predicted to double every two years to keep up with the demand for increased performance.
To meet these new requirements for performance and power, memory… Read More
The big challenge with audio is that there are so many standards. Some of this is for historical reasons since audio for mobile (such as mp3), for the home (Dolby 5.1) and for cell-phone voice encoding/decoding have all had very different requirements, different standard setters and so on. But gradually everything is coming together.… Read More
Just how many hands have touched your SoC design by the time it goes to manufacturing? Clearly the more hands that touch it, the more complex the design is, making it more difficult to meet your product requirements. The commercial semiconductor IP dilemma is that not only are you using the same IP as your competitors, you are exponentially… Read More
Joe Sawicki is the VP and General Manager at Mentor Graphics for the Design-to-Silicon Division where the Calibre product line is developed. We met today in Wilsonville, Oregon to review the challenges in IC design, processing and manufacturing.… Read More
T’is the season to be jolly…and to predict the next year’s semiconductor market.
KPMG does a regular survey of senior executives in semiconductor companies to get their outlook on the year ahead. The message this year is mixed. 41% of executives expected their business to grow by more than 5% next year, which sounds not too bad until… Read More
