This year’s SPIE Advanced Lithography is loaded with interesting keynotes and sessions. To help me narrow down what to see, I spoke with John Sturtevant. John is co-chair of the Design for Manufacturability through Design-Process Integration conference, and the director for technical marketing for RET products at Mentor Graphics.
San Jose Convention Center
All the cool kids will be there
I asked him how it’s changed since first introduced six years ago. John has been co-chair of the DFM conference for the last five years, so he has perspective. Here’s what he told me.
The conference saw a steady upsurge in number of papers in years 1-4, reflecting to a certain extent the hype that was DFM early on, as startups appeared on the scene, and “DFx” appeared on the business cards of an increasing number of engineers and VPs. As we separated the wheat from the chaff, most startups disappeared, and SPIE paper submissions to the conference dropped off somewhat to a steady state of around 40 papers. This was consistent with the predictions of Joe Sawicki in his invited paper in 2004, the second year of the conference.
The wheat which is left now grows in the fields of
[*=1]Multi-patterning implications to design and manufacturing
[*=1]Implications of EUV
[*=1]Design variability effects in manufacturing
[*=1]Restricted design rules
John recommends these papers in the DFM conference at SPIE:
Wednesday 10:40a, “Layout optimization through robust pattern learning and prediction in SADP gridded designs.” UC Santa Barbara and Mentor researchers present their study of placement-level optimization, including how to build a predictive model for layout pattern classification, and applying the model to find and eliminate printing hotspots. [8327-04]
Wednesday 1:50p, “Fully integrated litho aware PnR design solution.” STMicroelectronics and Mentor engineers present the STMicroelectronics back-end CAD solution for litho hotspot search and repair that is based on pattern matching and local re-route abilities in place and route tools. [8327-09]
Wednesday 2:30p, “Smart double-cut via insertion flow with dynamic design-rules compliance for fast new technology adoption.” Mentor and GLOBALFOUNDRIES engineers introduce an automatic redundant-via insertion flow. [8327-11]
Thursday 1:40p,“Thickness-aware LFD for the hotspot detection induced by topology.” Samsung and Mentor engineers present a method for advanced process window simulations with awareness of chip. [8327-24]
Thursday 2:00p, “The complexity of fill at 28nm and beyond.” Mentor and AMD engineers discuss modern fill challenges and advances in technology for 28nm. [8327-25]
And, if you’re interested to see how triple patterning will work for 14nm designs, go see “14nm M1 triple patterning”at 5:10p on Wednesday. [8326-38]Share this post via: