Immediately following Intel’s announcement that they expected Q4 revenue to come up short by $1B, Rory Read the new CEO of AMD, countered that they were on track to meet their original guidance (see article). Furthermore, “In 1Q and 2Q, maybe you see some manifestations, but I wouldn’t bet against the supply chain,”… Read More
SICAS (Semiconductor Industry Capacity Statistics) has released its 3Q 2011 data, available through the SIA at: SICAS data . Beginning with 2Q 2011 the SICAS membership list no longer includes the Taiwanese companies Nanya Technology, Taiwan Semiconductor Manufacturing Company Ltd. (TSMC) or United Microelectronics Corporation… Read More
LVS Challenges at Advanced Nodes
Accurate, comprehensive device recognition, connectivity extraction, netlist generation and, ultimately, circuit comparison becomes more complex with each new process generation. As the number of layers and layer derivations increases the complexity of devices, especially Layout Dependent… Read More
Conspiracy theories abound! The inside story of the Synopsys (SNPS) acquisition of Magma (LAVA) brings us back to the 1990’s tech boom with shady investment bankers and pump/dump schemes. After scanning my memory banks and digging around Silicon Valley for skeletons with a backhoe here is what I found out:
The Commission… Read More
3D IC design and what has come to be known as 2½D IC design, with active die on a silicon interposer, require new approaches to verification since the through silicon vias (TSVs) and the fact that several different semiconductor processes may be involved create a new set of design challenges
The power delivery network is a challenge… Read More
There was recently a forum discussion about the best low power techniques. Not surprisingly we didn’t come up with a new technique nobody had ever thought of but it was an interesting discussion.
First there are the techniques that by now have become standard. If anyone wants more details on these then two good resources are… Read More
Preventing electrical circuit failure is a growing concern for IC designers today. Certain types of failures such as electrostatic discharge (ESD) events, have well established best practices and design rules that circuit designers should be following. Other issues have emerged more recently, such as how to check circuits… Read More
Earlier this week I went to the Synopsys Interoperability Forum. The big news of the day turned out to be Synopsys wanting to be more than interoperable with Magma, but that only got announced after we’d all gone away.
Philippe Margashack of ST opened, reviewing his slides from a presentation at the same forum from 10 years … Read More
I’ve blogged about the Calibre family of IC design tools before:
Smart Fill replaced Dummy Fill Approach in a DFM Flow
DRC Wiki
Graphical DRC vs Text-based DRC
Getting Real time Calibre DRC Results with Custom IC Editing
Transistor-level Electrical Rule Checking
Who Needs a 3D Field Solver for IC Design?
Prevention is Better… Read More
The outlook for the global semiconductor market in 2011 has deteriorated from earlier in the year due to multiple factors including slower than expected economic growth in the U.S., debt crises in Europe and the Japan earthquake and tsunami. Recent forecasts have narrowed down to a range of -1.4% to 3.5%. In the first half of 2011,… Read More
