Design rules are at the heart of the interface between the foundry and semiconductor designers, which makes them so critical. Traditionally, design rules and DRC decks have been developed manually with no or little automation. Design rule definitions are written using WORD or other general purpose office tools, and DRC decks… Read More
If you’re headed to #53DAC (June 5-9 in Austin,TX) and are interested in learning more about FD-SOI, there will be lots of opportunities. Here’s a quick guide to get you started. … Read More
Continuing to find new ways to extend Moore’s Law, the foundry and technology leader is ready to show off its wafer level system integration prowess with two scalable platforms targeting key growth markets.
CoWoS® (Chip-On-Wafer-On-Substrate) goes after high-performance applications, providing the highest bandwidth and… Read More
Design starts are critical to the growth of the semiconductor industry so enabling them is a common theme on SemiWiki. One thing we have not covered in detail is multi-project wafer services (MPW) which is the equivalent of ride sharing through the initial mask and wafer process. Larger semiconductor companies already do this … Read More
A common SoC design methodology in current use starts with preparation of the physical floorplan — e.g., block/pin placement, global clock domain and bus signal planning, developing the global/local power distribution (and dynamic power domain management techniques). Decoupling capacitor estimated densities and… Read More
If you plan on visiting Solido (the world leader in EDA software for variation-aware design of integrated circuits) at the Design Automation Conference next month for a demonstration of Variation Designer, register online now and get an autographed copy of “Mobile Unleashed”. Such a deal!
Solido Variation Designer is used by… Read More
If you look back at the beginning of the ASIC business you will see that it was really a critical time in the semiconductor industry. It all began in the 1980s which coincidentally is when I started my career in Silicon Valley. General purpose integrated circuits ruled the market, forcing system designers to cobble together off-the-shelf… Read More
DAC is again going to be in Austin (reason enough to go), from June 6[SUP]th[/SUP]-8[SUP]th[/SUP] for the main event. A number of events caught my eye:
SPICE simulation is the workhorse tool for custom circuit timing validation and electrical analysis. As the complexity of blocks and macros has increased in advanced process nodes — especially with post-layout extraction parasitic elements annotated to the circuit netlist — the model size and simulation throughput… Read More
Mixed-signal design creates all sorts of interesting problems for implementation and verification flows, particularly when it comes to design for low power. We tend to think of mixed-signal as a few blocks like PLLs, ADCs and PHYs on the periphery of the design. Constrain and verify the digital power requirements up to analog … Read More
