If you look back at the beginning of the ASIC business you will see that it was really a critical time in the semiconductor industry. It all began in the 1980s which coincidentally is when I started my career in Silicon Valley. General purpose integrated circuits ruled the market, forcing system designers to cobble together off-the-shelf chips to build their products. The ultra-competitive nature of the semiconductor industry really is what drove the ASIC business model to where it is today (billions of chips). With everyone using off-the-shelf chips it is much harder to differentiate their products and make a profit, right?
Today it is déjà vu all over again with the DIY and Maker Movements cobbling together chips for a wide range of IoT devices that could go into high volume production in highly competitive markets.
Back then, getting an ASIC done was a highly negotiated process since you really did not know the size and complexity of your chip from the outset. I know of several examples where rough design specifications were literally delivered on scraps of paper or the legendary cocktail napkin. Today it is even more complicated with vast amounts of third party IP to choose from and many different foundry process alternatives to evaluate.
There is a nice chapter on the history of the ASIC business in our book “Fabless: The Transformation of the Semiconductor Industry” in case you are interested. If you are a registered SemiWiki member you can get a PDF copy of the book HERE. You can also get a paper or Kindle copy on Amazon.com.
Another interesting thing to note is that one of the driving forces of the ASIC business back in the 1980s was a stall in the growth of the semiconductor industry and the ensuing layoffs, much like the one we are experiencing today, which brings us back to IoT and the DIY and Maker Movements.
To get the DIY and Makers started on their ASIC adventure, Open-Silicon has a very nice landing page for IoT ASICs with white papers (Slash Time-To-Market and Risks: IOT SoC Platforms, IoT SoC Platform Demonstration_Cortex-M Series, Industrial IoT System Demonstration) and a replay of a joint ARM and Open-Silicon webinar: “Can a custom ASIC revolutionize your next IoT product?”.
To to make things even easier, Open-Silicon now has a web portal to dramatically reduce turnaround time for ASIC quotations. I tried it myself and found it to be intuitive and quite easy to use (and you don’t have to talk to a sales person). Just submit your systems requirements including your choices for IP, packaging, manufacturing process, system voltage, and power constraints. And did I mention you don’t have to talk to a salesperson?
And if you are going to #53DAC this year here is what Open-Silicon has planned for you:
Booth Demonstrations:IoT ASIC Platform–Demonstrates end-to-end communication between sensor hubs and a cloud platform through a gateway device. Depending upon the type of radio technology, the sensor hubs can be used outdoors, on the factory floor or inside a room. This Industrial IoT system setup is part of Open-Silicon’s Spec2Chip IoT Platform, which allows IoT ASIC designs to be evaluated at the system level.
28G SerDes Evaluation Platform–Enables the rapid deployment of chips and systems for high-bandwidth networks. The platform includes a full board with packaged 28nm test chip, software and characterization data. The chip integrates a 28Gbps SerDes quad macro, using physical layer (PHY) IP and meets the compliance needs of the CEI-28G-VSR, CEI-25-LR and CEI-28G-SR specifications.
HMC 2.0 Memory Controller ASIC IP Platform–Allows quick evaluation of the HMC technology and performance testing of the HMC links. Based on the Xilinx Virtex-7 FPGA, this platform includes a fully validated design that integrates an HMC controller exerciser functions.
2.5D SoC Solution Platform–Demonstrates a functional system-on-chip (SoC) solution featuring two 28nm logic chips, with embedded two dual core 1GHz ARM Cortex™-A9 ARM processors, connected across a 2.5D silicon interposer.
Breaking Through “The Memory Wall” – HBM IP Subsystem
Tuesday June 7, 3:30pm – 5:00pm, Ballroom G (IP Track: Evolving IP Interconnects & Verification)
Physical Planning of IO Interface for 3D Stacking of Packaged Devices
Monday, June 6, 5:00pm – 6:00pm, Exhibit Floor (Design/IP Track Poster Session)
Die Sizing Bound by Peripheral Bumps and IPs
Tuesday, June 7, 5:00pm – 6:00pm, Exhibit Floor (Design/IP Track Poster Session)
I hope to see you there!Share this post via: