SEMICON West 2022 and the Imec Roadmap

SEMICON West 2022 was held from July 12^th to 14^th at the Moscone Center in San Francisco.

On Monday the 11^th before the show, Imec held a technology forum at the Marriott Marquee right around the corner from the Moscone center. In recent years the Imec forums have shifted away from the process technology I cover to more of a system and application forum but there is still some process content.

During Luc Van den hove’s talk he presented the roadmap slide shown as figure 1.

Figure 1. Imec roadmap.

For all the talk in certain circles about the death of Moore’s law, the Imec roadmap presents over a decade of continued logic scaling.

At the N2 node Imec shows the transition to Gate-All-Around (GAA) nanosheets, this is underway now with Samsung introducing GAA nanosheets for their 3nm node and Intel and TSMC announcing GAA nanosheets for 2nm (Intel 20A). After two generations of nanosheets, Imec has a transition to Forksheets. Forksheets are a variant of nanosheets that reduces the track height of the cell. At this time, it isn’t clear to me how much traction Imec’s Forkseheet proposal is getting at the device manufacturers, I really haven’t seen any work on Forksheets outside of Imec. After two generations of Forksheet’s Imec has CFETs taking over. There is a lot of work being done on CFETs notably at Intel and TSMC. The last generation of CFETs introduces atomically thin sheets.

In Geert Van der Plas’ talk some more details were presented on the potential roadmap.

Figure 2 presents the transistor density that would result from the roadmap shown in figure 1.

Figure 2. Imec roadmap transistor density.

 As can be seen in figure 2., although density continues to increase the rate decreases to 1.2x to 1.3 per node.

Figure 3 presents some additional detail on the scaling roadmap with standard cell, backside, back-end-of-line and CMOS 2.0 innovations. Standard cell scaling is increasingly driven by Design-Technology-Co-Optimization (DTCO) such as single diffusion break, contact over active gate, forksheet wall, etc. The backside of the wafer is becoming a critical part of scaling with backside power delivery. BEOL will require new materials and patterning techniques to support the denser devices.

Figure 3. Transistor scaling innovations.

Figure 4 illustrates some options for the backside of the wafer, not only providing backside power delivery but also possibly incorporating active devices as well.

Figure 4. Backside options.

 On Tuesday morning I attended the “Unique Challenges Associated with Manufacturing 3D Devices and Structures Including GAA, 3D DRAM and 3D NAND” tech Talks moderated by Linx Consulting.

I only caught the end of the first speaker Nabil Mistkawi of Samsung’s talk, but I thought it was very interesting when he said at 7nm and below drying can require five steps to prevent pattern collapse, this really illustrates the fabrication difficulties presented by leading edge technologies.

Ian Brown of Screen went into more detail on pattern collapse and cleaning and drying challenges at the leading edge.

For logic devices shallow trench isolation/fin formation and post poly etch are critical steps. Nanosheets add a lot of surfaces some of them hidden and horizontal nanosheet release is very critical. 3D NAND silicon nitride removal needs to be a fast process, but you have to avoid silicon dioxide precipitation. DRAM active and capacitor formation are very critical.

Laplace pressure and surface tension can cause 3D structures to collapse. Spin dryers have been replaced with IPA dryers, but they are sensitive to surface state. Today modifying a hydrophilic surface to make it hydrophobic before drying is state-of-the-art for logic.

In the early days of the industry particles were removed by etching underneath them, then there was a transition to megasonics but below 65nm there were damage issues. Today spin cleaners are used but they can create damage if the pressure is too high. The best technique for drying currently available is super critical CO2 but it is slow and expensive due to the equipment cost.

Finally, Aviram Tam of Applied Materials discussed inspection and metrology challenges. 3D structures need a technique that can look into the structure. High energy eBeam offers the ability to look into a structure and characterize the structural dimensions versus depth. With the advent of EUV optical overlay is no longer accurate enough and eBeam is being looked at here as well.

Following the session, I walked the floor. The show has really shrunk from the days when it filled both the North and South Halls with this years show not using the South Hall. On Tuesday a lot of vendors were sitting in their booths with little or no traffic staring at their phone screens.

I walked the floor again Wednesday and there was a lot more traffic in the booths.

New York state had a big booth at the show and one thing that surprised me was the number of people in that booth both days, I mean how many people can be thinking about building a fan in New York?

Thursday I travelled back home.

Also Read:

ASML EUV Update at SPIE

The Lost Opportunity for 450mm

Intel and the EUV Shortage