SEMICON West – Applied Materials Selective Gap Fill Announcement

At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.

The discussion started off with PPACt, Power, Performance, Area, Cost and Time to market. This was also a key theme at the Imec Technology Forum and is of interest to me because as I mentioned in the Imec article my company has a simulation tool to provide process cost and cycle time. You can read my Imec article here.

Figure 1. PPACt.

With EUV entering volume production a key enabler to continued transistor shrinks is now on-line. But the problem is as transistors shrink and provide improved performance shrinking contacts, vias and interconnect lines are seeing increased resistance and that is becoming a bottleneck holding back the transistor gains.

Figure 2. Evolution of Transistor and Interconnect Scaling.

 A key issue is that with existing deposition technologies contacts require liner/barrier layers of high resistivity material and liner/barrier thicknesses are not scaling down. The result is the volume of actual conductor for small contacts is being squeezed down, for example at 7nm for a 20nm contact only about 25% of the volume is tungsten conductor (W). The current conformal deposition technologies also leaves a seam/gap in the middle of the contact.

Figure 3. Contact Scaling Paradox.

 What Applied Materials has developed is a multi-process platform that provides bottoms-up, selective, seam-free gap fill. This set of technologies can fill a contact or via from the bottom up, selectively so it only fills over metal – where there are gaps in the dielectric layer and does not require a barrier/liner. The result is a contact or via that is 100% conductor metal providing lower resistance.

The new Volta Selective W CVD system runs on the proven Endura platform and combines a metal surface treatment, a dielectric surface treatment and a selective W deposition on a single tool.

Because there are no seams the grains size is larger reducing grain boundary scattering – reducing the resistivity of the W. For a 35nm slot contact a 40% reduction in resistance is seen. Smaller contacts see even bigger resistance reductions.

Figure 4. Selective Fill Advantage.

This process is targeting vias because it only deposits over metal.

Applied Materials is getting strong traction on the new system and has already shipped >20 Volta Selective W systems to leading foundries worldwide.

This is a solution to a key problem that is growing in importance.

Also Read:

Imec Technology Forum and ASML

VLSI Symposium 2020 – Imec Buried Power Rail

Key Semiconductor Conferences go Virtual