Performance Testing and Analysis
Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die.
Agenda (BST)
12:00 Welcome and Introduction – Mike Bartley, Tessolve
12:00 Nick Heaton, Cadence Design Systems – SoC Verification in a Multi-chip,… Read More
Tuesday, February 21, 2023
8:00 am PT / 11:00 am ET
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