IITC 2024

IITC 2024
by Admin on 12-18-2023 at 8:52 pm

The 27th edition of the International Interconnect Technology Conference (IITC) will be held June 3-6, 2024 in San Jose, California.

The conference seeks papers on all aspects of BEOL/MOL interconnects and metallization, including design, unit process, integration and reliability, as well as how it applies to 2.5D/3D and Read More


DVClub Europe – Performance Testing and Analysis

DVClub Europe – Performance Testing and Analysis
by Admin on 04-03-2023 at 3:51 pm

Performance Testing and Analysis

Discuss the performance verification challenges posed by complex SoC with distributed cache from cluster, to interconnect to die-to-die.

Agenda (BST)

12:00 Welcome and Introduction – Mike Bartley, Tessolve

12:00 Nick Heaton, Cadence Design Systems – SoC Verification in a Multi-chip,Read More


WEBINAR: Introduction to UCIe™

WEBINAR: Introduction to UCIe™
by Admin on 02-13-2023 at 2:58 pm

Tuesday, February 21, 2023
8:00 am PT / 11:00 am ET

UCIe™ — Universal Chiplet Interconnect Express™ — is an open industry standard founded by the leaders in semiconductors, packaging, IP suppliers, foundries, and cloud service providers to address customer requests for more customizable package-level integration. The newly… Read More


How Deep Data Analytics Accelerates SoC Product Development

How Deep Data Analytics Accelerates SoC Product Development
by Kalar Rajendiran on 10-05-2022 at 8:00 am

Continuous Monitoring and Improvement Loop

Ever since the birth of the semiconductor industry, advances have always been at a fast pace. The complexity of SoCs have grown along the way, driven by the demanding computational and communication needs of various market applications. Over the last decade, the growth in complexity has accelerated at unforeseen rates, fueled… Read More


Synopsys Parasitic Extraction – Interconnect 2022

Synopsys Parasitic Extraction – Interconnect 2022
by Admin on 03-25-2022 at 1:16 pm

April 12, 2022
15:30 PM – 18:00 PM UTC +1
Virtual Experience

Why Attend?

Join us at the upcoming SPEX-I 2022 Workshops to learn about the latest features and flows to address signoff parasitic extraction challenges for advanced digital SoC designs or complex custom designs using Synopsys’ StarRC™ solution. In this workshop,… Read More


SEMICON West – Applied Materials Selective Gap Fill Announcement

SEMICON West – Applied Materials Selective Gap Fill Announcement
by Scotten Jones on 08-17-2020 at 5:00 pm

Applied Materials Selective Gapfill July 2020 Page 02

At SEMICON West, Applied Materials announced a new selective gap fill tool to address the growing resistance issues in interconnect at small dimensions. I had the opportunity to discuss this new tool and the applications for it with Zhebo Chen global product manager in the Metal Deposition Products group at Applied Materials.… Read More


Webinar – AI/ML SoC Memory and Interconnect IP Perspectives

Webinar – AI/ML SoC Memory and Interconnect IP Perspectives
by Tom Simon on 10-08-2019 at 10:00 am

For decades development work on Artificial Intelligence (AI) and Machine Learning (ML) was done on traditional CPUs and memory configurations. Now that we are in the “hockey stick” upturn in deployment of AI and ML, the search is on for the most efficient types of processing architectures. The result is a wave of development for… Read More


What are SOTIF and Fail-Operational and Does This Affect You?

What are SOTIF and Fail-Operational and Does This Affect You?
by Bernard Murphy on 05-22-2019 at 7:00 am

Standards committees, the military and governmental organizations are drawn to acronyms as moths are drawn to a flame, though few of them seem overly concerned with the elegance or memorability of these handles. One such example is SOTIF – Safety of the Intended Function – more formally known as ISO/PAS 21448. This is a follow-on… Read More


Supporting ASIL-D Through Your Network on Chip

Supporting ASIL-D Through Your Network on Chip
by Bernard Murphy on 09-20-2018 at 7:00 am

The ISO 26262 standard defines four Automotive Safety Integrity Levels (ASILs), from A to D, technically measures of risk rather than safety mechanisms, of which ASIL-D is the highest. ASIL-D represents a failure potentially causing severe or fatal injury in a reasonably common situation over which the driver has little control.… Read More


SEMICON West – Advanced Interconnect Challenges

SEMICON West – Advanced Interconnect Challenges
by Scotten Jones on 07-28-2017 at 12:00 pm

At SEMICON West I attended the imec technology forum where Zsolt Tokei presented “How to Solve the BEOL RC Dilemma” and the SEMICON Economics of Density Scaling session where Larry Clevenger of IBM presented “Interconnect Scaling Strategic for Advanced Semiconductor Nodes”. I also had the opportunity… Read More