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WP_Term Object
    [term_id] => 386
    [name] => Semiconductor Services
    [slug] => semiconductor-services
    [term_group] => 0
    [term_taxonomy_id] => 386
    [taxonomy] => category
    [description] => 
    [parent] => 0
    [count] => 1049
    [filter] => raw
    [cat_ID] => 386
    [category_count] => 1049
    [category_description] => 
    [cat_name] => Semiconductor Services
    [category_nicename] => semiconductor-services
    [category_parent] => 0

SEMICON West – Advanced Interconnect Challenges

SEMICON West – Advanced Interconnect Challenges
by Scotten Jones on 07-28-2017 at 12:00 pm

At SEMICON West I attended the imec technology forum where Zsolt Tokei presented “How to Solve the BEOL RC Dilemma” and the SEMICON Economics of Density Scaling session where Larry Clevenger of IBM presented “Interconnect Scaling Strategic for Advanced Semiconductor Nodes”. I also had the opportunity to meet with Tanaka Precious Materials and hear about their new Ruthenium precursor material. In this blog I will discuss back end of line (BEOL) scaling challenges and some possible solutions.

Zsolt Tokei – imec

The talk began with a quote from “Recent Advances in System-Level Interconnect Prediction” that “Interconnect are the Limiting Factor for Both Performance and Density”.

As interconnect pitches are shrinking both capacitance and resistance are increasing driving up the resistance-capacitance (RC) delay. The length of critical metals lines is related to contacted poly pitch (CPP) and CPP scaling has slowed putting more pressure on minimum metal pitch (MMP) to provide scaling. Slower CPP scaling makes the interconnect lines longer and more aggressive MMP scaling makes the lines narrower and both increase resistance.

Options to address RC include: geometry, the 3rd dimension and materials.

Geometric concepts include design rule optimization and the super via concept where instead of limiting vias to connecting metal level n to layer n+1, a super via connects metal n to metal n+2. For example, a standard via connects metal 1 to metal 2 and a super via connects from metal 1 to metal 3. By providing an additional option super vias can improve area and performance.

3D options include chip stacking with through silicon vias (TSV), sequential 3D where you form multiple layers of devices on one chip or integrating thin film transistors (TFT) into the back end. 3D with TSVs have cost and integration challenges, sequential 3D has integration and density challenges and TFT in the BEOL have performance and maturity challenges.

Copper has been the material of choice since the 130nm logic node due to its low resistivity. As dimensions scale down copper presents multiple challenges. First is that copper requires barrier and adhesion layers. The barrier and adhesion layers are made of relative high resistivity materials and the required thicknesses don’t scale well. At very small dimensions the percentage of the cross-sectional area of an interconnect that is copper is becoming smaller and the percentage that is barrier/adhesion layers is getting larger increasing the resistivity of the interconnect. The second problem with copper is that at very small dimensions the resistivity of copper increases due to scattering.

There is a lot of work being done on alternative materials that require less or no barrier/adhesion layer. Even if the new materials are higher resistivity by eliminating the barrier layer/adhesion layers a lower cross-sectional resistance may result. At the 10nm/7nm node we expect to begin to see cobalt filled contacts and local interconnect. Around the 5nm node we may begin to see ruthenium interconnects with no barrier/adhesion layer and despite ruthenium’s high resistivity it can outperform copper with a 2nm barrier at small dimensions. See figure 1.

Figure 1. Alternative metal examples. Source imec.

Larry Clevenger – IBM

Similar to the imec talk, this talk began with a statement of the problem, see figure 2.

Figure 2. RC scaling.

EUV can provide some relief in BEOL scaling, in addition to process advantages such as better resolution, single patterning and fewer masks, EUV can provide fewer ground rule restrictions, bi-directional versus uni-directional wiring and flexible wire widths.

Figure 3 illustrates the impact of EUV on design rules.

Figure 3. EUV versus 193i impact on design rules.

Other options for improving BEOL performance include

  • Getting signals into fat wire quickly trading off area for performance.
  • Use multiple redundant vias where resistance is important.
  • Reducing liner thickness with 1 to 2nm needed for 5nm.
  • When resistance is more important than capacitance use asymmetric line widths where the metal line is wider than the gap between lines.
  • Remove the barrier layer in the bottom of vias can reduce via resistance by 30%.
  • Air gaps can reduce capacitance by 20%.

As noted in the imec talk, cobalt and ruthenium are potential replacements for copper at smaller linewidths.

And finally heterogeneous integration with interposers can improve latency, bandwidth, cost and reliability.

Tanaka meeting
I also met with Tanaka Precious Metals at Semicon. Tanaka is developing a Ruthenium precursor for ALD and CVD deposition of Ruthenium. As both the imec and IBM presentations discussed Ruthenium is being investigated as a copper replacement around 5nm. Ruthenium has a higher bulk resistivity than copper but can be used without a barrier layers and doesn’t suffer from increasing resistivity as line widths shrink.

Tanaka Precious Metal is a 131-year-old $8.8 billion dollar privately held precious metal company. They are already a leader in precious metal sputter targets and gold bonding wire for the semiconductor industry.

Materials like Ruthenium can be deposited by physical vapor deposition (PVD) such as sputtering or deposited by chemical vapor deposition (CVD) or atomic layer deposition (ALD). Typical step-coverage for the three techniques is ALD > CVD > PVD.

The precursor Tanaka has developed is a liquid with a vapor pressure of around 0.2 torr at 100[SUP]o[/SUP]C, similar to other precursors. Deposition temperatures are 200[SUP]o[/SUP]C with a deposition rate of 2nm/min. Tanaka is doing a lot of work to improve deposition rates. They have shown CVD/ALD process with 5nm and 6nm barriers. The product is available for evaluation now.


Continued scaling will require careful optimization of the BEOL to minimize the negative impact on performance. New technique such as super vias, TFT in the BEOL, EUV and new materials such as ruthenium will all be needed to continue scaling.

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