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Open-Silicon SiFive and Customizable Configurable IP Subsystems

Open-Silicon SiFive and Customizable Configurable IP Subsystems
by Daniel Nenni on 02-01-2019 at 12:00 pm

After 8 SemiWiki years, 4,386 published blogs, and more than 25 million blog views, I can tell you that IP is the most read semiconductor topic, absolutely, and that trend continues. Another correlating trend (from IP Nest) is the semiconductor IP revenue increase in relation to the semiconductor market (minus memory) which more than doubled from 2006 to 2016 and is set to double again by 2026.

22939-ip-subsystems-semiconductor.jpg open-silicon

If you really want to know how important IP is ask an ASIC expert like Open-Silicon who specializes in chip differentiation by using customizable and configurable IP Subsystems. Here is a quick look at proprietary and third party IP that is an integral part of customizable system and physical design solutions offered by Open-Silicon:

By using an HBM2 IP Subsystem (controller + PHY + I/O), with silicon validation completed in TSMC’s FinFET and CoWoS technologies, customers can minimize the integration risk. Open-Silicon can also do a complete ASIC for you if time-to-market is a challenge.

Hybrid Memory Cube (HMC) is an innovative memory architecture in terms of performance, bandwidth, power efficiency, and reliability: 15x the performance of a DDR3 module, 70% less energy per bit than DDR3 DRAMs, and 90% less space than today’s RDIMMs.

Open-Silicon, a founding member of the Interlaken Alliance formed in 2007, launched the 8th generation of Interlaken IP core supporting up to 1.2 Tbps bandwidth. This high-speed chip-to-chip interface IP features an architecture that is fully flexible, configurable and scalable. Open-Silicon provides a complete Networking IP Subsystem which includes MAC IP + FlexE IP + PCS IP + MCMR FEC IP + Interlaken IP for ease of integration and as a one-stop solution to customers designing ASICs in TSMC FinFET technologies.

Investigating, evaluating, and integrating IP is rapidly becoming the biggest challenge of the SoC/ASIC industry. The success of a chip depends on the careful selection of reliable IP. Open-Silicon has a dedicated IP team that works with a wide variety of IP providers and is continually qualifying and ranking IP and updating a portfolio of recommended IP. The goal being to help you make informed IP decisions that differentiate your product, assure IP quality and reusability, and deliver first-time working silicon.

As you may have read Open-Silicon is now a SiFive company. It was a very disruptive move which greatly accelerated SiFive’s mission of becoming a fabless custom SoC powerhouse by leveraging Open-Silicon’s large customer base and ASIC implementation expertise.

The SiFive Tech Symposiums start this month in North America where you can spend time learning about the latest RISC-V offerings differentiated by customizable and configurable IP subsystems.

The RISC-V ISA has spawned a worldwide revolution in the semiconductor ecosystem by democratizing access to custom silicon with robust design platforms and custom accelerators. SiFive is fueling the momentum with myriad hardware and software tools for new and innovative RISC-V based solutions for IoT, AI, networking and storage applications. Attendance is free and includes lunch and plenty of time to meet and network with the speakers.

Mohit Gupta, SiFive Vice president of SoC IP, will be talking about all the offerings described above and more at the SiFive Tech Symposium at the Computer History Museum in Mountain View.

About Open-Silicon
Open-Silicon is a system-optimized ASIC solution provider that innovates at every stage of design to deliver fully tested IP, silicon and platforms. To learn more, please visit www.open-silicon.com

About SiFive
SiFive is the leading provider of market-ready processor core IP based on the RISC-V instruction set architecture. www.sifive.com

Also Read:

Ethernet Enhancements Enable Efficiencies

RISC-V End to End Solutions for HPC and Networking

A 2021 Summary of OpenFive

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