SPIE Advanced Lithography Conference – Imec and Veeco on EUV

The paper went on to summarize some recent Imec results exploring stochastics, but before discussing the results, Imec clearly stated in the paper that these are example results. That Imec’s environment is not as clean as a high-volume manufacturing fab and that may limit what they are able to achieve.

Figure 3 illustrates the stochastic cliffs for dense structures (a) and for non-dense structures (b). In the case of non-dense structures there is only a singe patterning cliff on the small CD side.

Figure 3. Dense patterns with double sided defect cliffs (a) and
non-dense patterns with single sided defect cliff (b).

In figure 4 an example of a 40nm pitch is shown. On the left side (a) the defect cliffs are characterized solely by a CD measurement tool limiting the minimum failure rate that can be measured. On the right side (b) an e-beam inspection eBI tool is used to measure lower failure rates. Note that the two cliffs touch at around 1ppm and although the process is within the Rayleigh limits for EUV, the process cannot achieve acceptable yield.

Figure 4. 40nm pitch pattern evaluation.

If the pitch is increased to 42nm now the defect cliffs move further apart, and the minimum defect rate moves down to around 1ppb possibly achieving acceptable yield depending on the process requirements.

Figure 5. 42nm pitch pattern evaluation.

Figure 4 and 5 are not meant to illustrate any absolute limits for EUV but rather to show the general behavior and characterization techniques needed to characterize the process performance. The key message here is a that CD SEM can measure down to ~1ppm and eBI can measure down to ~1ppb. Some applications may require down to ~1 part per trillion and may need an optical assessment tool.

Figure 6 illustrates dense line/spaces characterized with an optical inspection tool. Imec has previously shown the optical inspection can find microbridges of etched wafers such as was used here.

Figure 6. Dense line/spaces and the microbridge floor.

The left side of the figure shows the window for 32, 34 and 36nm pitch lines/spaces. The most interesting part is the right side that shows a minimum defect floor of microbridges even at larger CDs.

Further investigation shows that even though the cliffs are highly dependent on the pitch being printed, the defect floor is largely independent of pitch, see figure 7.

Figure 7. Defect floor versus pitch.

Looking at the micro-bridge floor, the defect size is found to be centered at 15nm with a tail out to about 60nm. The distribution is independent of pitch.

Evaluating three different photoresists the micro-bridge cliff was found to be dependent on the photoresist but the broken line cliff was not. All three photoresist were positive tone develop – chemically amplified resists and doses varied from 37 mJ/cm2 to 65 mJ/cm2. Two of the resists had the same micro-bridge defect floor and one resist had a higher floor. The higher floor is believed to be due to a difference in dispensing technique that meant that the third resist wasn’t filtered. The third resist also showed a slightly larger peak micro-bridge size at 20nm versus 15nm.

The paper went on to discuss several potential mechanisms. Since the defect floor sets a maximum achievable yield this is an area that needs more research.

The next paper discussion a mitigation technique for EUV defects.

Impact of SIS on roughness and stochastic nano-failure for EUVL patterning – Pieter Vanelderen
In addition to stochastic defects, challenges with EUV also include achieving acceptable pattern roughness at low doses and photoresist etch resistance.

Sequential Infiltration Synthesis (SIS) is an atomic layer deposition (ALD) like technique that smooths and hardens the photoresist, see figure 8.

Figure 8. Sequential Infiltration Synthesis

The objectives for SIS are:

• Roughness improvement through higher etch selectivity.
• Stochastic defect mitigation by healing micro-breaks.
• Local CD uniformity (LCDU) improvement.
• Apply SIS to industrially relevant cases.

In order to employ SIS the underlayer stack must be tuned to be SIS compatible with Spin-On-Glass (SOG) being the preferred underlayer.

A comparison of the etched pattern quality between an SIS and non-SIS process shows a 10% improvement for the SIS process, see figure 9.

Figure 9. SIS versus non SIS process.

SIS also opens up the window between the two stochastic cliffs, see figure 10.

Figure 10. Window between the stochastic cliffs with and without SIS.

In summary, SIS has shown:

• 10% improvement in roughness for etched features.
• A 2 order of magnitude reduction in micro breaks.
• A 20-30% improvement in local CD uniformity (LCDU)
• 20% smaller T2T .
• Reduced logic clip defectivity.

Still to be addressed is improved roughness on isolated features.

The final paper I will cover here concerns improved EUV masks.

Ion Beam Etching new absorber materials for sub 5nm EUV Masks – Narasimhan Srinivasan
Whereas DUV masks are transmissive, EUV masks are reflective masks. Currently EUV masks have a reflective layer made up of 40 mirror pairs of molybdenum/silicon each approximately 3nm thick covered by a patterned tantalum nitride absorber layer 60 to 70nm thick. The EUV radiation arrive at a 6-degree angle and as feature size shrink shadowing at the edge of the absorbers will be a growing problem. High NA EUV tools will also increase the arrival angel to 9-degrees increasing the problem.

In order to go to a thinner absorber layer to reduce shadowing a higher-k material is needed with Nickel (Ni) and Cobalt (Co) alloys showing the most promise. The problem is nickel and cobalt alloys have low volatility in Reactive Ion Etch (RIE) systems.

Figure 11. High-k EUV absorber material challenges.

Ion beam etching is the process of choice for Co and Ni. The characteristics of ion beam etching include:

• Ability to etch virtually any material with no chemistry dependence (physical etch).
• The same etch rate for dense and isolated features.
• Anisotropic etch (directional).
• Low temperature and energy down to 50 volts for low ion damage.

Veeco has shown that ion beam etching is viable for Co and Ni patterning.

Conclusion
With Samsung and TSMC ramping 7nm EUV processes into production, the era of EUV has begun. While EUV is successfully producing yielding 7nm wafers there is still a lot of work to do. As processes evolve to 5nm and 3nm stochastics defects, line roughness, dose, etch resistance, pellicles and EUV masks will all need to improve. The work described here from Imec and Veeco are important steps towards enabling EUV for future processes.

[1] Peter De Bisschop, “Stochastic printing failures in extreme ultraviolet lithography,” J. Micro/Nanolith. MEMS MOEMS 17(4), 041011 (2018), doi: 10.1117/1.JMM.17.4.041011