Webinar: ASICs Unlock Deep Learning Innovation

In March, an AI event was held at the Computer History Museum entitled “ASICs Unlock Deep Learning Innovation.” Along with Samsung, Amkor Technology and Northwest Logic, eSilicon explored how these companies form an ecosystem to develop deep learning chips for the next generation of AI applications. There was also a keynote presentation on deep learning from Ty Garibay, CTO of Arteris IP.

Over 100 people showed up, including myself, for an afternoon and evening of deep learning exploration and some good food, wine and beer as well. The audience spanned chip companies, major OEMs, emerging deep learning startups and research folks from both a hardware and data science/algorithm point of view. The event covered a lot of ground.

For those who couldn’t make it and interested parties around the world, there will be a webinar version of this event broadcast on May 2 from 8-9AM and 6-7PM Pacific time. I’ll be introducing the webinar and moderating the event. More than 400 people have registered already which is a record number for webinars I have been involved with, absolutely! You can sign up here:

ASICs Unlock Deep Learning Innovation HBM2/2.5D Ecosystem for AI Webinar
Deep learning algorithms, powered by neural nets, hold promise to automate our world in ways previously reserved for science fiction. Computers and cell phones that recognize us and talk to us, along with cars that drive us are just a few of the revolutionary products on the near horizon.

Practical implementation of this technology demands extreme performance, low power and efficient access to massive amounts of data. Advanced ASICs play a critical role in the path to production for these innovations. In fact, many applications cannot be realized without the performance and security that a custom chip provides.

What is needed is an implementation platform supporting 14nm and 7nm FinFET process nodes to address the challenges of deep learning.

Please join Samsung Electronics, Amkor, eSilicon and Northwest Logic as we explore a complete implementation platform for deep learning ASICs. The webinar will be moderated by Dan Nenni, CEO and founder of SemiWiki.

May 2, 2018
8:00-9:00AM or 6:00-7:00PM

8AM Registration and 6PM Registration

And here is my opening statement thus far:

Our insatiable need for data is driving IP address traffic growth to increase by 3X from 2015 to 2020. In the five years following 2015 there will be (as we are seeing now) a dramatic increase in the number of connected devices and the improvement in broadband speeds by almost 100%. This coupled with the increase in internet users and the huge amount of video that we are posting (and viewing) is driving semiconductor companies to build highly complex chips to meet the underlying requirements for bandwidth. WAN redesign: moving applications to the cloud and improving Ethernet switching speed from 40Gbps to 400Gbps by 2020.

Deep learning is a specific machine learning technique that uses neural network architectures, requiring large amount of data & compute power. There is a need for hardware acceleration for deep learning computation.

Deep learning is deployed today in all major data centers (cloud) and in devices (edge)

Deep Learning chips have 2 main functions: Training & Inference

Deep Learning applications can be divided into 3 main categories covering most industries:

• Image/Video: (object/image/facial recognition) Main industry: Automotive, Social Media, IoT, Advertising, Surveillance, Medical Imaging
• Voice: (speech recognition, language translation) Main industry: Social Media, Smart Homes, IoT
• Text/Data: (data mining, big data analytics, decision making) Main industry: Finance, cloud services, research.

Deep learning chipsets focus on 2 main functions – training and inference.

Training:
Training the neural network requires massive amount of training data, storage and compute power. Training ICs are typically in the cloud and some high-end devices.

Inference:
Uses the trained network to provide an ‘intelligent’ analysis/result which requires less data, storage and compute power than training. Inference ICs are typically in the AI devices and some in the cloud for low latency applications.

I hope to see you there!