Chip Design Problems Remain the Same, More or Less

For those who may not know me, here is a brief introduction. I started in the semiconductor business when RCA was still making vacuum tubes and I wrote EDA software before there was an EDA industry. I’ve designed and sold chips and developed, sold and used EDA tools at companies as big as General Electric and as small as seven people. So what have I learned through all those years and all those companies?

The problems with chip design remain the same, more or less.

The size of the problems and the penalty for getting it wrong have increased exponentially, though. That is courtesy of Moore’s Law. The effect is well known and I won’t revisit it. Let’s look at the problem set associated with chip design instead.

When I worked at RCA, we had a huge number of bipolar processes, and it was really hard to figure out which one to use. First-time-right silicon was a big, big challenge. There was a corporate mandate to reduce the number of processes and to re-engineer the design flow to use higher levels of abstraction to facilitate faster design that was less error prone.

Our solution was a symbolic layout system. The parameters for each circuit element were stored inside the symbol and the user did a “loose” layout of the chip. The layout was then sent to a “layout compiler” that would read the parameters and replace each circuit symbol with the polygons to implement that device. The whole thing then went to a layout compaction tool to get rid of the white space. We taped out the first chip with this system and got it done a lot faster. And it worked the first time. It was 1978.

A few years later, we were designing a new generation of single-chip microprocessors. There were several design groups working on various parts of the chip and assembling the whole thing was a huge problem. Without a good master plan, the pieces just didn’t fit very well, and critical-path timing issues kept getting in the way. A “paper” master plan was always developed and was out of date in about a day. The solution was to develop a hierarchical chip planning system that allowed manipulation of the plan at an abstract level. All the design groups accessed this same tool and kept the plan up to date. This system went live in 1980.

About a year later, in 1981, I was having a beer with a design manager who had just finished releasing a library of Texas Instruments TTL discrete parts that were now implemented in CMOS (to save power). We thought about all these components and all the work to get them taped out correctly (we still used actual magnetic tape by the way). What if we could strip the bond pads off these designs and release them as building blocks for on-chip macros? That day, we were inventing IP reuse and block-based design. We called the idea Silicon Circuit Board. The whole thing failed within six months – without a reuse methodology, reuse was, well, impossible.

Raising abstraction levels, re-using IP and automating design has been haunting us for a long, long time. Are there new and unique approaches to these problems? I think so. I’ll discuss that next time.

From Mike Gianfagna of eSilicon

Also read: Chip Design – Coming of Age in the Computer Age