SPIE 2021 – Applied Materials – DRAM Scaling

At the SPIE Advanced Lithography Conference in February 2021, Regina Freed of Applied Materials gave a paper: “Module-Level Material Engineering for Continued DRAM Scaling”. Applied Materials provided me with the presentation and was kind enough to set up an interview for me with Regina Freed.

I also spoke to Regina Freed last year after SPIE and wrote up her presentation on material enabled pattering available here. This work is an extension of that work specific to DRAM.

DRAM scaling is slowing, and new solutions are needed to continue to provide density improvements, see figure 1.

Figure 1. DRAM Nodes and Bit Density Trend.

 DRAM scaling presents multiple challenges:

1. Patterning – how to create the increasingly dense patterns.
2. Capacitors – evolving from a cylinder to a pillar structure, need to pattern high aspect ratios.
3. Resistance/Capacitance – bit lines and word lines resistance/capacitance improvements are needed for access speed.
4. Peripheral (Peri) Transistor – evolution from polysilicon gate with SiON oxide to High-K Metal Gate (HKMG).

Figure 2. DRAM Scaling Challenges.

This article will focus on 1. Patterning, and 2. Capacitors.

 Capacitor patterning has been recently done with cross self-aligned double patterning (XSADP) but is now evolving to even more complex cross self-aligned quadruple patterning (XSAQP). Another option has been spacer assisted patterning as disclosed by Samsung that can increase the hole density on a mask by 3x but needs an etch that equalizes the hole size. Recently EUV has entered use.

Authors note, Samsung is using EUV for one layer on 1z DRAM and expected using EUV for multiple layers for the 1α generation ramping now, SK Hynix is also expected to introduce EUV for their 1 α generation due this year.

There are several challenges when implementing EUV for DRAM:

1. Local Critical Dimension Uniformity (LCDU) – variations change electrical performance and etch aspect ratio.
2. Hole size – EUV is sensitive to hole size and has a narrow process window.
3. Thin resist – EUV photoresist is very thin and needs to be hardened.

The use of a thin deposition can harden the resist and a thick deposition can be used to shrink Critical Dimensions (CD). Spatially selective deposition on the top of the pattern can improve Line Edge Roughness (LER)/Line Width Roughness (LWR), notable weaknesses in EUV patterning. See figure 3.

Figure 3. Photoresist Improvements Using Deposition.

 For active area scaling EUV has defect issues at large CDs, instead you can etch small holes and then use precision lateral etch to open the feature in one direction shrinking the tip-to-tip distance. This technique eliminates the CD versus yield trade-off and enables ovals with larger contact landing areas, see figure 4.

Figure 4. Precision Lateral Etch for Active Patterning.

 A major problem with EUV is narrow process windows for acceptable stochastic defects. Directional etching gives you an additional knob for process design, if the middle of your process windows has opens and bridge, you can shift towards the side of the window that has bridges and then remove the bridges with directional etch, see figure 5.

Figure 5. Directional Etch to Remove Stochastic Defects.

Today’s capacitor pitch limits are >40nm which is also the current EUV limits for capacitor patterning. In the future smaller pitches will be required and process variability needs to be improved by >30% to enable scaling, see figure 6.

Figure 6. Capacitor Scaling Limited by Variation.

Reduced hard mask thickness and improved etch uniformity are both needed to enable this.

Today amorphous silicon (a-Si) is used for a hard mask, in the future doped silicon can provide better selectivity enabling thinner hard masks but creates hard to remove by-products, see figure 7.

Figure 7. Improved Hard Mask for Capacitor Scaling.

The issue with doped silicon for hard masks is it requires a special etch, the next generation process uses a high temperature etch. Photoresist is used to pattern an oxide hard mask; the oxide hard mask is then used in a high temperature etcher to pattern the doped polysilicon hard mask and finally the doped polysilicon hard mask is used to etch the capacitor. A level-to-level pulsing etch switching between etching and deposition steps allows aggressive chemistry usage for high-speed etching of the capacitor, see figure 8.

Figure 8. Improved Performance and Productivity.

The process innovations described above are expected to enable continued scaling of the current DRAM architecture.

Beyond 3 to 5 years a new DRAM architecture will be needed.

One interesting option we touched on briefly is a 3D approach where the capacitor changes from a vertical structure to a stacked horizontal structure.

In conclusion, Applied Materials continues to provide innovative integrated solutions for key patterning challenges to enable continued scaling, in this case for DRAM.

Also Read:

Kioxia and Western Digital and the current Kioxia IPO/Sale rumors

Intel Node Names

ISS 2021 – Scotten W. Jones – Logic Leadership in the PPAC era