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Semicon West

Semicon West
by Paul McLellan on 07-11-2012 at 7:08 pm

 I have been spending some time at Semicon West at the Moscone center the last couple of days. Since it was only a month ago that I was there for DAC, the first contrast is the size of the show. DAC didn’t fill Moscone South. Semicon fills Moscone South, and North, and the corridor between. And Moscone West on the other side of 4th street. Admittedly there is a co-located solar show but that is not a large fraction.

The big news of the show was Intel/ASML’s announcement that Intel is putting a lot of money into ASML for EUV (see below) and 45cm (18″) wafer technology. They were even one of the speakers at a fascinating session I attended.

I spent all morning today at a series of presentations about lithography. I blogged recently about how wafer prices going up faster than transistor densities (the scariest graph I’ve seen recently) which is essentially a graph and a story all about lithography, when you look under the hood.

Right now, continuing to use 193nm light and immersion lithography, everyone seems confident we can build 14nm chips (and smaller). But whether we can build them economically is the big question. At 20/22nm we have to double pattern the 1X layers (the higher levels of metal are on coarser grids and so don’t require it). We may have to triple pattern the first layer of metal since we really want both vertical and horizontal segments. Double patterning requires that you do some things twice and so costs more (although not twice as much). It also requires two masks so NRE is higher too, pushing up the fixed costs of taping out a design and manufacturing the first wafer.

There are three technologies that are in some level of development, and there were presentations about all of them. I will blog about each of them in more detail in the coming few days. But the executive summary is as follows:

 Extreme Ultra-Violet (EUV) is shorter wavelength light (14nm or so). At that wavelength the light can’t get through lenses (or even air) so we have to switch to reflective optics and reflective masks. We don’t yet have good ways to generate the light at high enough power but a lot of work is being done. We don’t yet have photoresist that is responsive enough. We can’t build defect-free mask blanks (and never will be able to). The big advantage is that we don’t need double patterning so only one mask per layer. But unless the throughput is high enough that isn’t a big enough advantage.

Next is DWEB, Direct Write Electron Beam. This is even better on the mask front. None of them. More like an old CRT TV used to write on the phosphor, this scans an electron beam across the photoresist and scans the design. The challenge again is getting throughput up, and having responsive enough photo resist. Plus the data handling is a challenge with thousands of beams writing simultaneously across a whole wafer (this isn’t reticle/stepper type technology).

 OK, so if lithography can’t hack it, how about we do something really spacey. How about we do directed self-assembly (DSA). This is something that a few academics have been looking at but suddenly a few years ago industry started to look at seriously. If you mix two substances that don’t mix (like oil and water) but that polymerize (so not oil and water, more like polystyrene) then if you just mix them and put them on a wafer you get a random pattern like a fingerprint. But if you first put down some guidance (hence “directed” self assembly) such as tracks on the wafer at 80nm spacing (which is easy today) and put the mixture in between, then instead of just forming random patterns, it lines up into nice 14nm tracks of alternating polymers. And if you build a trench and put some of the mixture in with the right ratio, it will form a few tiny holes. This is a long way from a chip, of course. But building lines and holes is the basis of chips. Then immersion lithography was considered out there not that long ago.


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